FinFET MONOS Memory Cell Trench Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of memory cells in semiconductor devices leads to increased field concentration at the tips or corners of fin structures, resulting in deterioration of rewrite endurance and charge storage characteristics, especially when high electric fields are applied for writing and erasing.
Innovation Solution
A semiconductor device with a FinFET having a split-gate type MONOS structure, where multiple fins are used to form a memory cell with deeper trenches between them, enhancing the effective channel width and reducing charge injection per unit area, thereby improving rewrite endurance and charge storage characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high electric field is applied for writing and erasing memory cell, then the amount of injected charge increases, but the rewrite endurance and charge storage characteristics deteriorate
Solution Approach 1:
The patent divides the channel region into multiple fins (first fin and second fin) within a single memory cell. This segmentation increases the total effective channel width without requiring higher electric fields, thereby reducing the stress on individual fin structures during write/erase operations and improving rewrite endurance while maintaining adequate charge injection capacity.
Solution Approach 2:
The patent introduces a deeper trench between the fins in the charge storage region compared to other regions. This local modification concentrates the charge storage capability in specific areas, allowing efficient charge trapping without requiring uniformly high electric fields across the entire structure, thus preserving charge storage characteristics while enabling sufficient charge injection.
2Area of stationary object
If miniaturization of memory cell is advanced, then the density increases, but the field concentration at fin tips or corners increases causing deterioration of rewrite endurance and charge storage characteristics
Solution Approach 1:
By using multiple fins per memory cell, the patent achieves miniaturization through increased vertical utilization rather than simply reducing individual fin dimensions. This segmentation approach maintains larger effective channel widths while reducing the physical footprint of each memory cell, avoiding excessive field concentration that would occur with single smaller fins.
Solution Approach 2:
The patent transitions from a planar single-fin structure to a three-dimensional multi-fin structure with selective trench depths. This dimensional change allows the memory cell to achieve higher density by utilizing vertical space more effectively while the deeper trenches between fins provide field management that prevents excessive concentration at fin tips, preserving reliability during miniaturization.
3Productivity
If multiple fins are used to increase effective channel width, then the charge injection per unit area decreases, but the rewrite endurance and charge storage characteristics improve
Solution Approach 1:
The patent creates a deeper trench specifically in the charge storage region between the fins, while maintaining shallower trenches or different structures in other regions. This local differentiation allows the charge storage area to efficiently trap charges from multiple fins without requiring proportionally higher injection amounts, as the deeper trench provides enhanced confinement and storage capacity in the critical charge retention zone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the rewrite endurance and charge storage characteristics of memory cells by reducing the charge injection amount and enhancing the effective channel width, while maintaining a constant read current, even under high electric field conditions.
Implementation Method 1
a silicon nitride film, and configured to trap electrons having a negative charge or holes having a positive charge
Implementation Method 2
the transistor is configured to have a three-dimensional structure, the field concentration is likely to occur at the tip or the corner of the fin
Data Source
AI summary
A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.