FinFET MOS Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
The integration of metal-insulator-metal (MIM) capacitors in the back-end-of-line (BEOL) of semiconductor chips introduces RC delays and restricts design flexibility, particularly in three-dimensional stacking applications, leading to image distortion in CMOS image sensor chips due to their location and bonding interface effects.
Innovation Solution
A FinFET MOS capacitor is integrated in the front-end-of-line (FEOL) with FinFET transistor devices, featuring a capacitor fin structure with heavily doped dummy source/drain regions and a dummy channel region, which enhances capacitance linearity and allows for greater capacitance without increasing the lateral footprint, using a capacitor gate structure separated by a thin gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MIM capacitors are integrated in the back-end-of-line (BEOL), then capacitance is achieved, but RC delays increase and design flexibility is restricted
Solution Approach 1:
The patent transitions from planar MIM capacitor structures to three-dimensional FinFET MOS capacitor structures. The FinFET configuration utilizes vertical fins extending from the substrate, creating a three-dimensional active area that increases capacitance without expanding lateral footprint. This dimensional change enables higher capacitance density while reducing RC delays by integrating the capacitor structure directly into the FEOL transistor fabrication process.
Solution Approach 2:
The patent merges the capacitor structure with the FinFET transistor structure by using the same fin region for both transistor channel and capacitor formation. The FinFET device combines the transistor function (with source, drain, and channel regions) and capacitor function (using the same fin structure with gate electrode) into a single integrated structure, eliminating the need for separate MIM capacitor blocks in the BEOL and reducing overall device area.
2Quantity of substance
If MIM capacitors are placed in BEOL, then capacitance is provided, but design flexibility is reduced due to location constraints
Solution Approach 1:
The FinFET structure serves multiple functions: it acts as both a transistor (with source, drain, and channel regions for switching) and a capacitor (using the same fin structure with gate electrode for charge storage). This multi-functionality eliminates the need for separate dedicated capacitor structures, providing design flexibility to use the same FEOL structure for both logic and memory functions, and enabling three-dimensional stacking configurations.
3Quantity of substance
If capacitor size is increased to achieve higher capacitance, then capacitance increases, but lateral footprint increases
Solution Approach 1:
The patent utilizes vertical three-dimensional FinFET structures where the fin extends upward from the substrate, increasing the active area in the vertical dimension rather than expanding laterally. The gate electrode wraps around the fin structure, providing gate control over the top and sidewalls, which increases capacitance density without increasing the lateral footprint of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces RC delays and enhances design flexibility, improving the performance and integration of semiconductor chips by achieving higher capacitance and linearity, thus minimizing image distortion in stacked CMOS image sensor chips.
Implementation Method 1
A FinFET MOS capacitor is integrated in the front-end-of-line (FEOL) with FinFET transistor devices, featuring a capacitor fin structure with heavily doped dummy source/drain regions and a dummy channel region, which enhances capacitance linearity and allows for greater capacitance without increasing the lateral footprint
Implementation Method 2
using a capacitor gate structure separated by a thin gate dielectric
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.