FinFET MOS Capacitor Structure for Lower RC Delay and Higher Capacitance
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Solution Overview
Problem
The integration of metal-insulator-metal (MIM) capacitors in the back-end-of-line (BEOL) of semiconductor chips introduces RC delays and restricts design flexibility, particularly in three-dimensional stacking applications, leading to image distortion in CMOS image sensor chips due to their location and bonding interface effects.
Innovation Solution
A FinFET MOS capacitor is integrated in the front-end-of-line (FEOL) with FinFET transistor devices, featuring a capacitor fin structure with heavily doped dummy source/drain regions and a dummy channel region, which enhances linearity and capacitance by using a thin capacitor gate dielectric, allowing for greater capacitance without increasing lateral footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MIM capacitors are integrated in the BEOL, then capacitance is achieved, but RC delays increase and design flexibility is restricted
Solution Approach 1:
The patent transitions from planar BEOL capacitor integration to vertical FEOL FinFET-based capacitor structures. By utilizing the third dimension (vertical fin structures) and integrating capacitors in the FEOL rather than BEOL, the design achieves capacitance while reducing RC delays through shorter interconnect paths and improved spatial utilization.
Solution Approach 2:
The patent merges capacitor and transistor functions into shared FinFET structures. The same fin structures serve both as transistor channels and capacitor elements, eliminating the need for separate capacitor regions and reducing overall device area while maintaining design flexibility.
2Productivity
If MIM capacitors are placed at bonding interfaces in stacked chips, then integration is achieved, but image distortion occurs due to RC delays
Solution Approach 1:
The patent moves capacitor integration from the bonding interface level (BEOL) to the FEOL level within the same chip substrate. This vertical repositioning reduces the distance between capacitor and active circuit elements, minimizing RC delays that cause image distortion while maintaining three-dimensional stacking capability.
Solution Approach 2:
The patent introduces heavily doped dummy source/drain regions as intermediary elements between the capacitor gate and channel. These doped regions serve as charge storage sites that improve capacitance linearity and reduce RC effects, thereby mitigating image distortion while preserving integration benefits.
3Quantity of substance
If capacitor gate dielectric thickness is reduced, then capacitance increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent modifies the electrical properties of the dummy source/drain regions through heavy doping rather than relying solely on reducing gate dielectric thickness. By changing the doping concentration parameter, the patent achieves improved capacitance and linearity while avoiding the manufacturing precision challenges associated with ultra-thin dielectrics.
Solution Approach 2:
The patent applies heavy doping specifically to the dummy source/drain regions adjacent to the channel, creating localized high-capacitance zones. This localized modification enhances capacitance where needed without requiring uniform reduction of gate dielectric thickness across the entire structure, thereby reducing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of FinFET MOS capacitors in the FEOL reduces RC delays and enhances design flexibility, improving chip integration and reducing image distortion in stacked CMOS image sensor chips by achieving higher capacitance with controlled doping and dielectric structures.
Implementation Method 1
The capacitor fin structure (104) comprises a pair of dummy source/drain regions (106a, 106b) spaced apart by a dummy channel region (110). The dummy channel region (110) is heavily doped with a doping concentration greater than that of the pair of dummy source/drain regions (106a, 106b).
Implementation Method 2
A capacitor gate stack (120) is disposed between the dummy source/drain regions (106a, 106b) overlying the dummy channel region (110). The capacitor gate stack (120) comprises a capacitor gate structure (118) separated from the capacitor fin structure (104) by a capacitor gate dielectric (108).
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated circuit containing a transistor, a sidewall spacer, a semiconductor region with multiple doped layers, an insulator layer, and a metal layer. The transistor having a channel region, an insulating layer surrounding three sides of the channel region, and a conductive layer surrounding three sides of the channel region. The semiconductor region has an outer sidewall facing a side of the sidewall spacer opposite from the transistor. The insulator layer surrounds three sides of the semiconductor region. The metal layer surrounds three sides of the insulator layer. The semiconductor region has a width equal to a width of the channel region the transistor along a first line, and the semiconductor region has a second width less than a second width of the channel region of the transistor along a second line.