FinFET MOS Capacitors for Low Inductance Decoupling
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Solution Overview
Problem
Existing decoupling capacitor fabrication processes for integrated circuits increase the number of fabrication steps without benefiting from the steps used in fin field effect transistor processes, leading to inefficiencies in integrating capacitors close to device elements, which results in increased inductance and slower response times due to longer transmission lines.
Innovation Solution
The method involves doping a capacitor region in a semiconductor-on-insulator substrate, forming doped semiconductor fins, and integrating a dielectric layer to increase capacitor area without expanding its footprint, while also forming undoped semiconductor fins for transistors, allowing for a high-k dielectric layer to separate the terminals and reduce fabrication costs by integrating capacitors within the FET process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are placed close to device elements, then inductance is reduced and response time is improved, but fabrication process complexity increases
Solution Approach 1:
The patent merges the capacitor fabrication process with the finFET fabrication process by using the same doping and etching steps to create both the fin structures for transistors and the finned structures for capacitors. This integration eliminates separate fabrication steps, reducing overall process complexity while enabling close placement of capacitors to devices.
Solution Approach 2:
The patent makes the fin etching process universal by using it for both transistor fin formation and capacitor fin formation. The same masking and etching steps serve dual purposes, creating structures that function as both active transistor elements and capacitor electrodes, thereby simplifying the fabrication process.
2Quantity of substance
If capacitor area is increased to enhance capacitance, then capacitance value is improved, but capacitor footprint is increased
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional finned structures. By extending the capacitor electrodes vertically into multiple fins, the effective capacitance area is increased without expanding the horizontal footprint on the chip. The capacitance is enhanced through the cumulative surface area of multiple fins within the same footprint.
Solution Approach 2:
The patent nests multiple fin structures within the capacitor footprint, creating a compact arrangement where numerous thin fins are positioned closely together. This nested configuration maximizes the effective capacitance area by packing multiple conductive surfaces into a small horizontal space, thereby increasing capacitance without increasing footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitance by increasing conductor area, reduces fabrication time and costs, and allows decoupling capacitors to be placed arbitrarily close to device elements, minimizing inductance and improving response times.
Implementation Method 1
doping a capacitor region of a top semiconductor layer in a semiconductor-on-insulator substrate
Implementation Method 2
oxidizing a surface of a transistor region of the semiconductor layer to produce an oxidized layer; etching the oxidized layer to produce fins of oxidized semiconductor
Data Source
AI summary
Methods for capacitor fabrication include doping a capacitor region of a semiconductor layer in a semiconductor-on-insulator substrate; partially etching the semiconductor layer to produce a first terminal layer comprising doped semiconductor fins on a remaining base of doped semiconductor; forming a dielectric layer over the first terminal layer; and forming a second terminal layer over the dielectric layer in a finFET process.