FinFET Magnetoresistive Memory Cell Layout for Leakage Control
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Solution Overview
Problem
Miniaturization of cell transistors in magnetoresistive memory devices leads to increased off-leakage current and parasitic resistance due to short channel effects, making it difficult to maintain device performance and current drive efficiency.
Innovation Solution
The implementation of a multi-gate device layout with fin-shaped active areas and parallelogram-shaped contact regions, where the active areas are inclined and perpendicular to the gate electrodes, maximizing the overlap of front and back gates for effective channel control and reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If cell transistor size is miniaturized to reduce cell area, then cell area is reduced, but off-leakage current increases due to short channel effect
Solution Approach 1:
The invention transitions from planar single-gate transistors to three-dimensional multi-gate FinFET structures. The FinFET configuration extends the gate control into the vertical dimension, allowing the gate to control the channel from multiple surfaces (front, back, and sidewalls), thereby maintaining effective channel control even when the planar footprint is minimized.
Solution Approach 2:
The active area is segmented into multiple fins that extend vertically from the substrate. Each fin acts as an independent channel region controlled by gates, allowing the total channel width to be distributed across multiple segmented structures rather than a single planar region, improving control while maintaining compact area.
2Area of moving object
If cell transistor size is miniaturized to reduce cell area, then cell area is reduced, but parasitic resistance increases due to smaller contact regions
Solution Approach 1:
The contact regions are extended into the vertical dimension by forming contacts on the sidewalls of the FinFET structure. This allows additional contact area to be achieved without increasing the planar footprint, as the contacts utilize the vertical surfaces of the fins to reduce parasitic resistance.
3Reliability
If multi-gate device is implemented to suppress short channel effect, then channel control is improved, but device layout complexity increases
Solution Approach 1:
The FinFET structure employs an asymmetric configuration where the gate wraps around three sides of the vertical fin structure rather than covering all four sides. This asymmetric multi-gate design provides effective channel control while simplifying the fabrication process compared to fully symmetric multi-gate structures, reducing layout complexity.
4Length of moving object
If gate length is reduced to miniaturize transistor, then transistor size is reduced, but short channel effect worsens
Solution Approach 1:
The invention compensates for reduced gate length by extending gate control into the vertical dimension. The FinFET structure provides gate control over the channel from front, back, and sidewall surfaces, effectively increasing the total gate-controlled surface area and improving electrostatic control despite shorter horizontal gate lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the short channel effect, enhances current drive, and simplifies manufacturing processes by allowing for bidirectional current flow and reduced property variation, enabling high-performance magnetoresistive memory devices with minimized cell area.
Implementation Method 1
a magnetoresistive effect element (MTJ) having a lower end connected to the drain side contact region and an upper end connected to a bit line
Data Source
AI summary
According to one embodiment, there is provided a magnetoresistive memory device. The memory device includes active areas arranged on a semiconductor substrate, resistance change elements arrayed to matrix in an X direction and a Y direction above the substrate, and selective transistors provided to correspond to the respective resistance change elements. A plurality of gate electrodes of the selective transistors are spaced apart at regular intervals in the X direction and arranged along the Y direction. Each of the active areas is provided to cross two of the gate electrodes adjacent to each other, such as to be along the X direction at a portion crossing the gate electrodes, and formed to be inclined with respect to the X direction between the adjacent gate electrodes.