FinFET Multi-Metal Gate Segmentation for Leakage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional FinFETs face limitations in performance, particularly in controlling the channel region and reducing punch-through source-drain leakage current due to the limited work function of the gate structure, which is insufficient for high-frequency operations.

Innovation Solution

The method involves forming multiple metal gate structures with different work functions by creating a hard mask layer with long stripes on a semiconductor substrate, forming sub-fins and corresponding metal gate structures in trenches, and using these structures to cover the side and top surfaces of the fins, thereby enhancing control over the channel regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional single gate structure is used in FinFET, then the device structure is simple and easy to manufacture, but the control ability over the channel region is insufficient and punch-through source-drain leakage current cannot be effectively reduced

Engineering Contradiction:
Improvecontrol ability over channel regionVSAvoidgate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate structure is segmented into multiple independent metal gate structures (first metal gate structure, second metal gate structure, third metal gate structure) with different work functions, each controlling different channel regions. This segmentation allows independent optimization of gate control for different fin regions, improving overall channel control ability while managing the complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different metal gate structures are applied to different channel regions based on local requirements. The first metal gate structure with a specific work function controls the first channel region, the second metal gate structure controls the second channel region, and the third metal gate structure controls the third channel region. This local quality approach optimizes carrier injection and control for each specific region, addressing the insufficient control ability of conventional uniform gate structures

Inventive Principle:
Principle #3Local quality

2Productivity

If the critical dimension is reduced to continue scaling, then transistor density increases, but the conventional MOS field-effect transistor structure becomes unable to satisfy performance needs

Engineering Contradiction:
Improvetransistor densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The invention transitions from planar 2D channel control to 3D vertical fin structure with multi-gate control. The FinFET structure with vertical fins and multiple gate structures wrapping around the fins provides three-dimensional channel control, maintaining device performance as critical dimensions are reduced and enabling continued scaling by exploiting the vertical dimension

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate structure uses composite material approach by combining multiple metal materials with different work functions in different gate structures. This composite gate system provides tailored electrical characteristics for different channel regions, enabling the device to maintain high performance at reduced critical dimensions through optimized carrier control in each region

Inventive Principle:
Principle #40Composite materials

3Reliability

If a single work function gate is used, then the gate structure is simple, but the drive current and device performance at high frequencies are limited

Engineering Contradiction:
Improvedrive current and high-frequency performanceVSAvoidmetal gate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate system is segmented into multiple metal gate structures with different work functions optimized for different functions: the first metal gate structure controls the first channel region, the second metal gate structure controls the second channel region, and the third metal gate structure controls the third channel region. This segmentation enables independent optimization of drive current and high-frequency performance for different regions while managing complexity through modular architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the work function parameter of the gate structures by using different metal materials. The first metal gate structure has a first work function, the second metal gate structure has a second work function, and the third metal gate structure has a third work function. This parameter change allows optimization of carrier injection and channel control for different operating conditions, improving drive current and high-frequency performance

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9755080B2Fin field-effect transistor
Publication Date: 2017.09.05 SEMICON MFG INT (SHANGHAI) CORP
  • US9755080B2 patent drawing
  • US9755080B2 patent drawing
  • US9755080B2 patent drawing

AI summary

A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.