FinFET Source/Drain Multi-Layer Structure for Lower DIBL and Resistance
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Solution Overview
Problem
The challenge of forming reliable semiconductor structures, particularly FinFETs, arises from the difficulty in fabricating complex and small-scale circuits due to advancements in IC processing and manufacturing, which require novel structures to improve performance.
Innovation Solution
A method involving a gate-replacement process is employed to fabricate FinFETs, utilizing a multi-layer source/drain structure formed through epitaxial growth and deposition processes, including the formation of dummy gate structures, hard mask layers, gate spacers, and replacement metal gate structures, along with dielectric and blocking layers to enhance the semiconductor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar MOSFET devices are scaled down to smaller feature sizes, then functional density increases, but manufacturing reliability deteriorates due to fabrication difficulties
Solution Approach 1:
The patent transitions from planar MOSFET devices to FinFET structures by adding vertical dimensionality. The fin structure extends vertically from the substrate, allowing the channel to be controlled from multiple sides by the gate, thereby increasing functional density while maintaining manufacturability through a three-dimensional architecture that better utilizes the vertical space.
Solution Approach 2:
The source and drain regions are segmented into multiple epitaxial layers with different compositions and doping characteristics. This segmentation allows each layer to perform specific functions: the first layer provides mechanical support and lattice matching, while the second layer optimizes electrical conductivity, thereby improving manufacturing reliability through specialized functional zones.
2Quantity of substance
If FinFET structures are fabricated with smaller feature sizes, then functional density increases, but fabrication complexity increases
Solution Approach 1:
Dummy gate structures are formed prior to the actual gate fabrication to define the channel region and provide a reference structure for subsequent processing steps. This preliminary action simplifies the overall fabrication sequence by establishing critical dimensions early in the process.
Solution Approach 2:
Epitaxial liner layers are introduced as intermediary structures between the fin structure and the source/drain regions. These liner layers facilitate controlled epitaxial growth, provide lattice matching to reduce defects, and enable precise doping profiles, thereby simplifying the fabrication of the source/drain junctions.
3Reliability
If multi-layer source/drain structures are formed through epitaxial growth, then conductivity improves, but process complexity increases
Solution Approach 1:
Different epitaxial layers are assigned different local qualities: the first source/drain epitaxial layer has composition and doping optimized for mechanical support and lattice matching, while the second layer has properties optimized for electrical conductivity. This local differentiation allows each layer to excel at its specific function without compromising the other.
Solution Approach 2:
The source/drain structure employs composite epitaxial layers with different semiconductor compositions (e.g., SiGe, SiC, or doped silicon layers). These composite materials combine the advantages of different semiconductor systems: mechanical stability from one material and high conductivity from another, achieving superior overall performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and conductivity of FinFETs by reducing drain-induced barrier lowering and on-resistance, facilitating better electrical performance and manufacturing consistency.
Implementation Method 1
A first source/drain epitaxial layer is formed in the fin structure and adjacent to the gate structure. A second source/drain epitaxial layer is formed over the first source/drain epitaxial layer.
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a source/drain (S/D) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the S/D epitaxial layer. The semiconductor structure includes a contact plug barrier formed over the S/D epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.