FinFET Multi-Layer Spacer Structure for RF Cut-Off Frequency
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Solution Overview
Problem
Conventional FinFETs exhibit higher parasitic capacitance between the gate and source/drain features, leading to reduced cut-off frequency and limited applications, particularly unsuitable for radio frequency (RF) applications.
Innovation Solution
A semiconductor device with a multi-layer spacer formed along the sidewalls of the FinFET's gate feature, interposed between the gate and source/drain features, which increases the distance and suppresses electromagnetic coupling, allowing for enhanced cut-off frequency and suitability for both logic and RF applications by forming FinFETs with different spacer thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FinFET structure is formed with the gate feature directly adjacent to source/drain features, then device scalability and gate controllability are improved, but parasitic capacitance between gate and source/drain features increases
Solution Approach 1:
A dielectric spacer is introduced as an intermediary layer between the gate feature and source/drain features. This spacer physically separates the gate from the source/drain regions, reducing electromagnetic coupling and parasitic capacitance while preserving the three-dimensional FinFET structure's gate controllability advantages
2Productivity
If the gate feature is positioned close to source/drain features for compact device layout, then device density and scalability are improved, but cut-off frequency is reduced due to higher parasitic capacitance
Solution Approach 1:
The dielectric spacer acts as a mediator that enables compact device layout while maintaining high cut-off frequency. By providing electrical isolation between gate and source/drain features, the spacer reduces parasitic capacitance effects that would otherwise limit high-frequency performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer spacer significantly reduces parasitic capacitance, enhancing the cut-off frequency and enabling FinFETs to be suitable for both logic and RF applications by optimizing spacer thicknesses for specific use cases.
Implementation Method 1
a higher parasitic capacitance coupled between the gate feature and each of the pair of drain/source features when compared to the planar MOSFET. Such a higher parasitic capacitance generally results from more electromagnetical coupling induced between a sidewall of the gate feature and each of the pair of drain/source features
Data Source
AI summary
A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.