FinFETs with Multiple Fin Heights for Performance Balancing
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Solution Overview
Problem
As integrated circuits continue to downscale, FinFETs need to maintain high drive currents with smaller dimensions, and existing methods struggle to optimize transistor performance across different device regions due to uniform fin heights.
Innovation Solution
A method for forming semiconductor fins with varying fin heights, allowing for differentiated FinFETs in different device regions, where shallow trench isolation regions are recessed to create fins of distinct heights, enabling independent tuning of device performance and balancing p-type and n-type FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If uniform fin heights are used across all device regions, then manufacturing simplicity is maintained, but transistor performance cannot be optimized across different device regions
Solution Approach 1:
The patent applies local quality by creating different fin heights in different device regions through selective STI recessing. Specifically, first STI regions are recessed to a first depth while second STI regions are recessed to a second depth, resulting in first fins with a first height and second fins with a second height. This allows each region to be optimized for its specific function (e.g., higher fins for drive current, lower fins for leakage control) while maintaining a unified manufacturing process flow.
2Power
If larger fin dimensions are used, then drive current increases, but device area and scaling limitations worsen
Solution Approach 1:
The patent transitions from planar transistor geometry to three-dimensional FinFET structure by creating fins with significant height relative to width. The FinFETs are formed over a semiconductor substrate with gate electrodes conformally covering the fins, creating a vertical channel that increases effective channel width without increasing planar footprint. This dimensional change enables higher drive current while maintaining small device area and supporting continued scaling.
3Adaptability or versatility
If p-type and n-type FinFETs use the same fin height, then manufacturing is simplified, but performance balancing between transistor types becomes difficult
Solution Approach 1:
The patent enables performance balancing by assigning different fin heights to p-type and n-type FinFETs through selective STI recessing. The first fins with first height can be assigned to one transistor type while second fins with second height serve the other type. This local differentiation allows optimization of each transistor type's performance characteristics (e.g., matching drive currents, balancing threshold voltages) while using a single etch process with spatially selective masking to maintain manufacturing efficiency.
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.