FinFET and Nanosheet Gate Structure for Multi-Vt Density Limits
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Solution Overview
Problem
Existing methods for fabricating multi-threshold voltage IC devices face challenges in optimizing device density and performance due to increased channel lengths, which consume valuable space and reduce device speed and ON current.
Innovation Solution
The semiconductor structure incorporates n-type and p-type FinFET devices, along with an n-type nanosheet FET device, allowing for customizable threshold voltage (Vt) adjustments through fin structure dimensions and work function metal layer selections to meet different Vt requirements for core and memory circuits without impacting other devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel length is increased to achieve higher threshold voltage devices, then threshold voltage is improved, but device density and fabrication area are reduced
Solution Approach 1:
The patent applies local quality by introducing specific doping concentrations and types in different regions of the channel. High concentration doping is applied in source/drain regions while lower doping is used in the channel region, creating localized property variations that enable threshold voltage control without extending channel length.
Solution Approach 2:
The patent changes multiple parameters including doping concentration, doping type, and fin dimensions to control threshold voltage. By adjusting these parameters locally in different device regions, the patent achieves multi-threshold voltage devices without increasing overall channel length, thereby maintaining high device density.
2Reliability
If channel length is increased to achieve higher threshold voltage devices, then threshold voltage is improved, but device speed and ON current are reduced
Solution Approach 1:
The patent creates local quality variations through selective doping in source/drain regions versus channel regions. This localized doping strategy enables threshold voltage adjustment without proportionally increasing channel length, thereby preserving carrier transport speed and ON current characteristics.
Solution Approach 2:
The patent transitions from controlling threshold voltage through one-dimensional channel length extension to using multi-parameter control including doping concentration, doping type, and fin cross-sectional dimensions. This dimensional parameter expansion enables independent optimization of threshold voltage and device speed.
3Reliability
If channel length is increased to achieve higher threshold voltage devices, then threshold voltage is improved, but fabrication space is consumed
Solution Approach 1:
The patent employs local quality control through region-specific doping concentrations and types. By concentrating dopant atoms in source/drain regions rather than extending the channel, the patent achieves threshold voltage modulation within the same footprint area, maximizing space utilization.
Solution Approach 2:
The patent utilizes multiple controllable parameters including doping concentration, doping species, and fin geometry to adjust threshold voltage without changing device area. This parameter diversity enables threshold voltage tuning while maintaining compact device dimensions for high-density integration.
Data Source
AI summary
A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.