FinFET and Nanostructure FET Integration on Single Substrate
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Solution Overview
Problem
Current integrated circuits using FinFETs and nanowire FETs on different substrates occupy more space and have limited current capacity due to the use of single nanostructures per stack, which restricts their performance in compact devices.
Innovation Solution
Integrating FinFETs and nanostructure FETs on a single bulk substrate, where the nanostructure FETs include multiple nanostructures per stack, increasing current capacity and reducing space requirements by forming a stack of at least two nanostructures between source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FinFETs and nanowire FETs are formed on different substrates, then device functionality is achieved, but space occupation increases
Solution Approach 1:
The patent merges FinFET and nanowire FET fabrication processes onto a single substrate by forming nanowire stacks in trenches adjacent to FinFET structures. This integration allows both transistor types to coexist on the same substrate, reducing the total area required compared to using separate substrates while maintaining the functional advantages of both device types.
2Ease of manufacture
If a single nanowire per nanowire stack is used, then fabrication simplicity is maintained, but current capacity is limited
Solution Approach 1:
The patent segments the current conduction path by creating multiple discrete nanowires within each nanowire stack. Instead of relying on a single nanowire, the structure divides the channel into multiple parallel nanowires (e.g., three nanowires per stack), which collectively provide higher current capacity while maintaining a relatively simple fabrication process using sequential epitaxial growth and selective removal.
Solution Approach 2:
The patent transitions from a two-dimensional planar view to a three-dimensional vertical structure by forming nanowire stacks that extend vertically within trenches. This vertical stacking allows multiple nanowires to be packed into a compact footprint, increasing current capacity without proportionally increasing the lateral area occupied.
3Quantity of substance
If multiple nanostructures per nanostructure stack are implemented, then current capacity increases, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming alternatingbilayer structures with suspended sections before final device completion. The alternatingbilayer epitaxial growth creates precursor structures that are subsequently processed to form the multi-nanowire stacks. This preliminary structuring simplifies the overall fabrication sequence despite the complexity of the final multi-nanowire configuration.
Data Source
AI summary
An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.