FinFET Gate Structure with Narrow-Middle Profile
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Solution Overview
Problem
Existing FinFET devices and manufacturing methods have limitations in achieving optimal performance due to issues with gate profile and spacer protection during the processing of FinFET devices, leading to inefficiencies in complexity and cost in semiconductor integrated circuit manufacturing.
Innovation Solution
A method for forming FinFET devices involving the creation of a dummy gate with a narrow-middle profile, followed by spacer formation and replacement with a gate having a similar profile, which protects spacers during recess formation and improves filling quality, reducing parasitic capacitance and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional planar gate structure is used, then the manufacturing process is simple, but the parasitic capacitance between gate and source/drain is high
Solution Approach 1:
The gate structure is segmented into multiple portions (first gate portion, second gate portion, third gate portion) with different widths along the channel direction. This segmentation allows each portion to be optimized independently, reducing parasitic capacitance at source/drain regions while maintaining control over the channel
Solution Approach 2:
The gate structure employs asymmetric width portions - the first and third gate portions have greater widths than the second gate portion. This asymmetric design reduces parasitic capacitance at the source and drain regions where wider gate portions are positioned, while the narrower middle portion maintains effective channel control
2Reliability
If spacer formation is performed before gate patterning, then the spacer protection is improved, but the gate profile control becomes difficult
Solution Approach 1:
A dummy gate structure is formed preliminarily before the actual gate structure. This dummy gate serves as a protective template during spacer formation and recess etching processes, ensuring proper spacer protection while allowing subsequent replacement with the final asymmetric gate structure for precise profile control
Solution Approach 2:
The dummy gate acts as an intermediary element between the spacer formation process and the final gate structure. It provides the necessary protection during manufacturing while being replaceable by the final asymmetric gate, decoupling the protective function from the control function
3Ease of manufacture
If the gate width is uniform throughout the channel, then the manufacturing process is simple, but the operational speed is limited by high parasitic capacitance
Solution Approach 1:
Different portions of the gate structure have different widths tailored to local requirements. The wider first and third gate portions are positioned at source/drain regions to reduce parasitic capacitance, while the narrower second gate portion maintains channel control. This local quality variation improves operational speed without significantly complicating manufacturing
Data Source
AI summary
Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate over the substrate. Besides, the gate include a first portion, a second portion overlying the first portion and a third portion overlying the second portion, and the critical dimension of the second portion is smaller than each of the critical dimension of the first portion and the critical dimension of the third portion.