FinFET Channel Neck Structure for Off-Leakage Suppression
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Solution Overview
Problem
Current methods for preventing current leakage in FinFETs, such as using a silicon-on-insulator substrate or forming a punch-through stopper, are complex and difficult to control, and there is a need for a more effective solution that does not require expensive materials or complicated processes.
Innovation Solution
The manufacturing process involves forming fin structures with a bottom part and an upper part over a substrate, where the bottom part is trimmed to have a smaller width than the upper part, and an isolation insulating layer is formed to expose the upper part, allowing for the formation of a dummy gate structure and source/drain structures, which are then replaced with metal gate structures, effectively creating a channel region with a neck portion that suppresses off-leak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a silicon-on-insulator substrate is used to prevent current leakage, then current leakage is reduced, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies local quality by creating a neck portion only in specific regions where current leakage needs to be suppressed, rather than using expensive SOI substrates throughout the entire device. The neck portion is formed by selective trimming of the fin structure at the channel region, creating a localized high-resistivity path that prevents off-leak current while maintaining standard substrate usage elsewhere.
Solution Approach 2:
The patent replaces expensive SOI substrates with a cost-effective alternative: a standard substrate combined with a geometric modification (neck portion) of the fin structure. This approach uses inexpensive manufacturing processes (trimming and isolation layer formation) to achieve the same electrical isolation effect that would otherwise require costly specialized substrates.
2Object-affected harmful factors
If a punch-through stopper or oxide layer is formed below the channel region to reduce current leakage, then current leakage is suppressed, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the essential function of current leakage suppression from complex buried structures (punch-through stoppers or oxide layers) and implements it through a simpler geometric feature: the neck portion of the fin structure. By removing the need for additional buried layers and focusing on the fin geometry itself, the solution reduces structural complexity while maintaining the isolation function.
Solution Approach 2:
Instead of adding complex structures below the channel region to prevent leakage, the patent inverts the approach by modifying the fin structure itself to create the isolation effect. The neck portion is formed by trimming the fin width at the channel region, creating a natural barrier to current flow without requiring additional layers or complex burial structures.
3Object-affected harmful factors
If the fin structure width is reduced uniformly to suppress current leakage, then off-leak current is reduced, but transistor performance deteriorates
Solution Approach 1:
The patent applies local quality by creating a neck portion only in the channel region where current leakage needs to be suppressed, while maintaining the full fin width in the source and drain regions. This localized trimming ensures that transistor performance is preserved in the source/drain areas while achieving current leakage suppression in the channel region through the narrowed neck portion.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.