FinFET Device Structure With Nested Dielectric Layers
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Solution Overview
Problem
The production of FinFET transistors faces challenges due to their small size, which complicates manufacturing and conflicts with the need for increased drive current without occupying more chip area, as larger gate widths are required for higher drive currents but are difficult to achieve in reduced semiconductor device sizes.
Innovation Solution
A method involving multiple dielectric layers and hardmask layers is used to pattern and recess the substrate, forming fin spacers and semiconductor strips that support the formation of fins with controlled dimensions, allowing for increased drive current without expanding chip area, by using advanced patterning techniques such as dry etching and photoresist processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gate width is increased to increase drive current, then drive current capability is improved, but chip area occupied increases
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures by forming vertical fins extending from the substrate. This dimensional change allows the gate to control current flow through multiple surfaces (top and sidewalls of fins), effectively increasing the drive current capability without proportionally increasing the chip area footprint.
Solution Approach 2:
The patent employs multiple nested dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) with progressively smaller widths forming a nested structure. This nesting approach enables precise control of fin spacing and dimensions while maintaining compact chip area utilization.
2Area of stationary object
If FinFET size is reduced to decrease chip area, then chip area is reduced, but manufacturing precision becomes more difficult
Solution Approach 1:
The patent forms a first hardmask layer and patterns it into strips before forming the fin structures. This preliminary patterning establishes precise spacing guidelines that guide subsequent fin formation processes, ensuring accurate fin spacing even at reduced device dimensions.
Solution Approach 2:
The patent introduces multiple intermediary dielectric layers and hardmask layers as mediators between the substrate and final fin structures. These intermediary layers provide controlled spacing and protection during manufacturing processes, enabling precise fin spacing control in small-scale FinFET devices.
3Manufacturing precision
If multiple dielectric layers are added to control fin spacing, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the dielectric structure into multiple segmented layers (first dielectric layer, second dielectric layer, third dielectric layer), each serving specific functions in the fin formation process. This segmentation allows independent optimization and control of each layer's properties and thickness, improving manufacturing precision while managing complexity through modular design.
Data Source
AI summary
Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further comprises forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion, and forming a first spacer and a second spacer over the first dielectric layer, wherein the first spacer and the second spacer are on opposite sides of the first raised portion, and wherein the sidewalls of the first spacer and the second spacer are substantially orthogonal to the top surface of the substrate.