FinFET Nonvolatile Memory Cell With Nested Floating Gate
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Solution Overview
Problem
The semiconductor industry faces challenges in producing non-volatile memory cells with floating gates on finned structures, such as FinFETs, which require innovative methods to achieve high packing density and improved performance and reliability.
Innovation Solution
The method involves forming a first fin and a second fin on a substrate, with a floating gate positioned between the fins, a control gate and select gate formed over the floating gate, and a tunnel dielectric and interpoly dielectric used to encapsulate the floating gate, allowing for charge storage and improved memory functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar memory cells are used, then manufacturing is simpler, but packing density is lower
Solution Approach 1:
The patent transitions from planar (2D) memory cell structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change allows memory cells to utilize vertical space, significantly increasing packing density while maintaining manufacturability through established FinFET fabrication processes
2Reliability
If floating gate memory cells are added to FinFET structures, then non-volatile storage capability is achieved, but device complexity increases
Solution Approach 1:
The patent implements a nested gate structure where a floating gate is positioned within or adjacent to the control gate structure. The floating gate is embedded in the FinFET region while the control gate extends over both the FinFET and non-FinFET regions, creating a nested configuration that provides non-volatile storage capability without requiring completely separate gate structures
Solution Approach 2:
The control gate structure serves multiple functions: it acts as the control gate for the FinFET device and simultaneously provides the gate structure for the floating gate memory cell. This multi-functional design achieves non-volatile storage capability while reducing overall device complexity by eliminating the need for completely separate gate structures
3Productivity
If FinFET structures are used, then packing density and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the substrate into distinct FinFET regions and non-FinFET regions, allowing different fabrication processes to be applied to each region. The fins are formed in specific regions while other regions maintain planar structures, enabling selective application of complex FinFET manufacturing steps only where needed, thereby reducing overall manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reduced gate length and increased width, enhancing packing density, vertical scalability, select gate drive current, and program and erase reliability compared to planar memory cells, while maintaining non-volatile storage capabilities.
Implementation Method 1
A tunnel dielectric is formed adjacent to the first fin, and a floating gate is formed adjacent to the first fin such that the tunnel dielectric is between the floating gate and the first fin
Data Source
AI summary
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.