FinFET Non-Volatile Memory Cell Gate Coupling Ratio
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in size, there is a need to enhance the reliability of memory cells in non-volatile memory devices to improve performance and reduce production costs while maintaining compatibility with existing manufacturing processes like FinFET.
Innovation Solution
The non-volatile memory design incorporates a substrate with fins, a floating gate, and a control gate, along with an inter-gate dielectric layer and contact slots, which increases the gate coupling ratio and allows for precise alignment and manufacturing compatibility with FinFET processes, using materials like silicon oxide, silicon nitride, and metal-containing materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of memory devices are reduced to increase integration level, then device density increases, but reliability of memory cells deteriorates
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional FinFET structures, utilizing vertical fins extending from the substrate. This dimensional change allows increased gate control over the channel while maintaining reduced device footprint, thereby improving reliability without sacrificing density.
Solution Approach 2:
The patent implements nested gate structures where control gates are positioned over floating gates, and both are integrated within the FinFET structure. This nested arrangement maximizes the use of vertical space, enhancing gate coupling ratio while maintaining compact device dimensions for high density.
2Reliability
If new manufacturing processes are developed to improve memory cell reliability, then reliability increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent designs the FinFET structure and gate stack to serve multiple functions: the fins provide both mechanical support and active channel regions, while the gate structures serve dual purposes in charge storage and control. This multi-functionality reduces the need for additional specialized process steps, maintaining manufacturing simplicity.
Solution Approach 2:
The patent employs preliminary formation of the FinFET structure and gate stacks before final memory cell assembly. By pre-establishing the three-dimensional fin structures and gate configurations, the patent simplifies subsequent processing steps and ensures reliable device performance without requiring complex post-assembly operations.
Data Source
AI summary
A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.