FinFET Metal Gate Offset Spacer Layout for Gate Length Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in optimizing the gate length of MOSFETs, particularly in advanced CMOS structures, where differences in gate length between NMOS and PMOS transistors complicate the lithography process and increase manufacturing costs due to variations in dummy gate lengths and side wall shapes, especially in fine pattern processing beyond the 22 nm generation.
Innovation Solution
The introduction of offset spacers between the metal gate electrodes and side wall spacers allows for arbitrary control of the metal gate electrode formation region, enabling optimized gate length regardless of the inner wall size of the side wall spacers, thus facilitating regular pattern formation and reducing manufacturing burdens.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different gate lengths are used for NMOS and PMOS transistors to optimize performance, then transistor performance is improved, but lithography process complexity increases and manufacturing costs rise
Solution Approach 1:
The gate structure is segmented into multiple components: dummy gate electrode, side wall spacer, and offset spacer. This segmentation allows independent optimization of gate length for NMOS and PMOS transistors while maintaining a unified lithography pattern, thereby improving transistor performance without increasing lithography complexity
Solution Approach 2:
The invention transitions from controlling gate length solely in the planar dimension to utilizing the vertical dimension through multi-layer spacer structures. The offset spacer is positioned between the side wall spacer and metal gate electrode, creating a three-dimensional structure that enables differential gate length control without affecting the two-dimensional lithography pattern
2Adaptability or versatility
If dummy gate electrodes are removed to form metal gate electrodes, then advanced CMOS structure is achieved, but variations in side wall shapes and gate lengths occur
Solution Approach 1:
The offset spacer is formed in advance, before the metal gate electrode is deposited. This preliminary action establishes a precise spatial reference that guides the subsequent metal gate electrode formation, ensuring consistent gate length and side wall shape across all transistors regardless of the dummy gate removal process
Solution Approach 2:
The offset spacer acts as an intermediary element between the side wall spacer and the metal gate electrode. It mediates the relationship between these components, providing a buffer that compensates for variations introduced during dummy gate removal and ensuring uniform gate length control
3Length of moving object
If fine pattern processing is performed beyond 22 nm generation, then device scaling is achieved, but manufacturing burden increases due to pattern regularity requirements
Solution Approach 1:
The multi-component gate structure serves multiple functions simultaneously: it enables fine pattern processing for device scaling, maintains pattern regularity for ease of manufacturing, and provides independent gate length optimization for different transistor types. The same basic structure (dummy gate + side wall spacer + offset spacer) is universally applied across all transistors regardless of their specific gate length requirements
Data Source
AI summary
A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.