FinFET OTP Memory Cells with Divided Active Regions
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Solution Overview
Problem
Conventional programmable resistive memory cells using MOS or diodes as program selectors face challenges in reducing cell size and cost, particularly due to the large size requirements for delivering program current and the complexity of processing steps involved.
Innovation Solution
The use of FinFET structures as program selectors in standard FinFET technologies allows for the construction of programmable resistive devices and memories with reduced cell size and cost, utilizing diodes or MOS devices with P+ and N+ implants, and extended source/drain regions to function as program selectors or OTP elements, leveraging existing FinFET processes without additional masks or steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS or diodes are used as program selectors in conventional programmable resistive memory cells, then the programming function can be achieved, but the cell size becomes large due to the size requirements for delivering program current
Solution Approach 1:
The patent transitions from planar MOS structures to three-dimensional FinFET structures. The FinFET's vertical fin configuration increases the effective channel area without increasing the planar footprint, allowing sufficient program current delivery while reducing cell size. The fin structure provides greater surface area for current flow in the vertical dimension while maintaining a compact lateral footprint.
Solution Approach 2:
The patent changes the geometric parameters of the program selector by using FinFET structures with controlled fin height, width, and thickness. By adjusting these dimensional parameters, the device achieves optimal balance between program current capability and cell size reduction. The fin dimensions are specifically engineered to deliver required program current while minimizing the occupied area.
2Reliability
If MOS or diodes are used as program selectors, then programming can be performed, but the processing complexity and cost increase
Solution Approach 1:
The patent utilizes standard FinFET structures that serve multiple functions: they act as both the program selector and the active device for memory operations. The FinFET structure is engineered to perform both selection and programming functions, eliminating the need for separate dedicated program selector components and reducing overall device complexity.
Solution Approach 2:
The FinFET structure inherently provides the necessary program current delivery capability through its vertical fin geometry, eliminating the need for additional external components or complex circuitry. The structure serves itself by using its geometric configuration to achieve both size reduction and sufficient current delivery without requiring additional processing steps.
3Power
If larger program selector devices are used to deliver required program current, then sufficient current can be delivered, but the cell size increases
Solution Approach 1:
The patent resolves this contradiction by moving the area expansion from the lateral plane to the vertical dimension. The FinFET's tall, thin fin structure provides increased surface area for current flow vertically, while maintaining a compact lateral footprint. This dimensional transition allows high program current delivery without increasing the planar cell size.
Solution Approach 2:
The patent employs composite material structures in the FinFET, combining different materials for the fin body, gate, and source/drain regions. This material composition optimization enhances current delivery efficiency per unit area, allowing sufficient program current with reduced device dimensions. The material stack is engineered to maximize electrical performance while minimizing physical size.
Data Source
AI summary
An One-Time Programmable (OTP) memory is built in at least one of semiconductor fin structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one fin. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one fin can be built on a common well or on an isolated structure that has at least one MOS gate dividing fins into at least one first active region and a second active region.