FinFET OTP Memory Bit Cell Layout with Dual-Use PODE Gate

Solution Overview

Problem

Current one-time-programmable (OTP) non-volatile memory technologies face challenges in minimizing power requirements and footprint while maintaining performance, particularly in the compact structure of semiconductor devices.

Innovation Solution

The proposed solution involves configuring a dummy Poly-on-OD-Edge (PODE) gate electrode as a functional programming transistor in a bit cell of the memory, reducing the number of transistors required and thereby minimizing the bit cell area while maintaining performance, by utilizing FinFET devices and optimizing the structure of gate electrodes to serve dual functions of protection and programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If traditional OTP memory structure is used, then programming functionality is achieved, but bit cell area is large

Engineering Contradiction:

Improvebit cell areaVSAvoidnumber of transistors

Core Design Contradiction:

Area of moving objectVSDevice complexity

Solution Approach 1:

The dummy PODE gate electrode is merged with the programming transistor gate electrode, combining the edge protection function with the programming function into a single structure. This eliminates the need for separate dummy transistors at the edges of the memory array, reducing the bit cell area while maintaining both protection and programming capabilities.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The PODE gate electrode is designed to serve dual functions: protecting functional transistors at the edge from breakdown during programming operations and serving as the programming transistor gate electrode itself. This multi-functionality reduces the total number of transistors required in the bit cell structure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Area of stationary object

If more transistors are used for programming, then programming capability is enhanced, but footprint increases

Engineering Contradiction:

Improvememory array footprintVSAvoidprogramming capability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The dummy PODE gate electrode is merged with the programming transistor gate electrode, combining the edge protection function with the programming function into a single structure. This eliminates the need for separate dummy transistors at the edges of the memory array, reducing the bit cell area while maintaining both protection and programming capabilities.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The PODE gate electrode is designed to serve dual functions: protecting functional transistors at the edge from breakdown during programming operations and serving as the programming transistor gate electrode itself. This multi-functionality reduces the total number of transistors required in the bit cell structure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If conventional memory structure is used, then functionality is maintained, but power consumption is high

Engineering Contradiction:

Improvepower consumptionVSAvoidstructure complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The dummy PODE gate electrode is merged with the programming transistor gate electrode, combining the edge protection function with the programming function into a single structure. This eliminates the need for separate dummy transistors at the edges of the memory array, reducing the bit cell area while maintaining both protection and programming capabilities.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The PODE gate electrode is designed to serve dual functions: protecting functional transistors at the edge from breakdown during programming operations and serving as the programming transistor gate electrode itself. This multi-functionality reduces the total number of transistors required in the bit cell structure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12052859B2Non-volatile memory device with reduced area

Publication Date: 2024.07.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.