FinFET Oxide Etch Selectivity via High-Temperature Ion Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming finFETs face challenges in etch rate modulation, particularly due to the lack of etch selectivity between dummy oxide and the box layer, leading to issues like S/D to channel short or low breakdown voltage.
Innovation Solution
The method involves performing a high-temperature ion implantation on finFETs with a thermally grown oxide layer, followed by an etch process to remove the masking layer without affecting the buried oxide layer, thereby modulating the etch rate and improving selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a standard etch process is used to remove dummy oxide, then the dummy oxide is removed, but the box layer underneath the spacer is also etched away causing S/D to channel short or low breakdown voltage
Solution Approach 1:
The patent applies preliminary action by performing high-temperature ion implantation on the box layer before the etch process. This pre-treatment modifies the box layer's properties so that during subsequent etching, the box layer becomes resistant to removal while the dummy oxide is selectively removed. The ion implantation creates a damaged layer that etches differently, enabling the etch process to distinguish between dummy oxide and box layer, thus preventing box layer removal and avoiding S/D to channel shorts.
Solution Approach 2:
The patent changes physical parameters of the box layer through high-temperature ion implantation. The ion implantation process alters the structural and chemical properties of the box layer, creating a damaged layer with different etch characteristics. This parameter change enables selective etching where the dummy oxide is removed at a different rate than the modified box layer, achieving the required etch selectivity to prevent device defects.
2Manufacturing precision
If etch selectivity between dummy oxide and box layer is improved through ion implantation, then box layer protection is achieved, but process complexity increases
Solution Approach 1:
The patent merges the ion implantation step with the existing etch process sequence. Rather than adding completely separate process modules, the ion implantation is integrated as a preparatory step that works in conjunction with the subsequent etch process. This merging approach achieves enhanced selectivity while minimizing the increase in overall process complexity, as the ion implantation and etching are coordinated as a combined process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively modulates the etch rate, preserving the integrity of the buried oxide layer and enhancing the selectivity of the etch process, which helps in preventing shorts and maintaining high breakdown voltage in finFETs.
Implementation Method 1
performing a high-temperature ion implant to the semiconductor device
Implementation Method 2
high-temperature ion implant
Implementation Method 3
performing an etch process to remove the masking layer from atop each of the plurality of fins
Data Source
AI summary
A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.