FinFET Gate Oxide Thickness Monitoring via Cox Capacitance
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Solution Overview
Problem
Existing methods for monitoring gate oxide thickness in FinFET platforms suffer from significant errors due to the unique structure of FinFET, which complicates the measurement of capacitance and leads to inaccurate thickness determination.
Innovation Solution
A method involving a FinFET platform-based device structure with specific metal structures and AC voltage application to measure capacitance Cox, allowing direct measurement of gate oxide thickness using the formula Tox=ε*S/Cox, where ε is the dielectric constant and S is the area of the gate oxide layer facing the active region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the RM AA method is used to monitor gate oxide thickness in FinFET platform, then the measurement process is simple, but the measurement precision is poor due to incomplete blocking of real structure and large capacitance from gate sidewall to metal layer
Solution Approach 1:
The patent segments the gate structure into distinct regions: the gate electrode, gate oxide layer, and separately identifies the gate sidewall region. By creating a test structure that isolates the gate oxide capacitance from the gate sidewall capacitance, the measurement method separately characterizes each component. This segmentation allows accurate measurement of gate oxide thickness without interference from the large sidewall capacitance that plagues conventional RM AA method in FinFET platforms.
2Reliability
If the gate oxide thickness is reduced to suppress short-channel effect, then the device performance is improved, but the measurement of capacitance becomes more complex and error-prone
Solution Approach 1:
The patent introduces a specially designed test structure as an intermediary between the actual FinFET device and the measurement system. This test structure includes a gate electrode overlying a gate oxide layer formed on a semiconductor substrate, with specific configurations that isolate and control the capacitance measurement. The test structure acts as a mediator that simplifies the measurement of gate oxide capacitance while maintaining relevance to actual device performance, thereby reducing measurement complexity and error despite the reduced gate oxide thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise measurement of gate oxide thickness, reducing measurement errors and providing accurate monitoring of the gate oxide layer thickness in FinFET platforms.
Implementation Method 1
obtaining the capacitance Cox of the gate oxide layer
Implementation Method 2
Tox=ε*S/Cox, here Tox represents the thickness of the gate oxide layer, E is a dielectric constant of the gate oxide layer
Data Source
AI summary
The present application provides a method for monitoring a gate oxide thickness: providing a device structure comprising a gate structure, a gate oxide layer under the gate structure, source and drain regions and a base region; applying a voltage −Vdd on the gate structure so that an accumulation layer is formed between the source and drain regions, applying a small AC voltage on the basis of the gate voltage −Vdd; grounding the source and drain regions; applying a voltage signal close to 0 potential on the base region; obtaining the capacitance Cox between the gate structure and the base region by testing; and obtaining the thickness of a gate oxide layer according to the formula Tox=ε*S/Cox. This technique accurately monitors the thickness of the gate oxide layer, and avoids those errors caused by existing methods.