FinFET Parasitic Extraction Using 3D Geometry Analysis
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Solution Overview
Problem
The challenge lies in accurately extracting parasitic capacitance and resistance values from non-planar integrated circuit (IC) designs, which are complex due to their three-dimensional geometries, making traditional two-dimensional representations inadequate for verifying device performance and manufacturing.
Innovation Solution
A verification tool that computes parasitic capacitance and resistance values based on the three-dimensional geometries of conductors and dielectrics in IC designs, using a process description file to analyze cut-outs and apply numerical solvers to determine capacitance and resistance values, specifically for FinFET devices by dividing cut-out surface areas into smaller units and considering spatial coordinates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional two-dimensional representations are used for non-planar IC designs, then verification and manufacturing processes remain simple, but extraction accuracy of parasitic elements becomes insufficient
Solution Approach 1:
The patent transitions from two-dimensional polygon representations to three-dimensional object representations for non-planar IC designs. This dimensionality change enables accurate capture of vertical structures like FinFETs, through-holes, and stacked devices, resolving the contradiction by improving extraction accuracy while managing verification complexity through automated 3D processing workflows
2Measurement precision
If three-dimensional objects are used to represent non-planar IC designs, then extraction accuracy of parasitic elements improves, but computing resources and engineering time increase significantly
Solution Approach 1:
The patent segments the 3D IC structure into discrete objects (conductors, dielectrics, vias) with defined geometric properties. This segmentation enables modular processing where each object type can be handled by specialized extraction routines, reducing overall engineering time while maintaining 3D accuracy for parasitic element calculation
Solution Approach 2:
The patent changes the representation parameters from 2D polygon coordinates to 3D object parameters including volume, surface area, and spatial positioning. This parameter transformation enables accurate parasitic extraction while the system optimizes computation by calculating only the necessary parameters for each object type rather than full 3D simulations
3Productivity
If non-planar devices are designed with three-dimensional geometries, then transistor density and performance improve, but design and verification difficulty increases
Solution Approach 1:
The patent employs 3D object representation to capture the vertical dimension in non-planar devices, enabling accurate modeling of FinFET channels, multi-pole structures, and through-silicon vias. This approach maintains high transistor density while managing design complexity through automated verification tools that process 3D geometries
Solution Approach 2:
The patent creates simplified 3D geometric models that replicate the essential electrical characteristics of complex non-planar devices. These copied geometric representations enable verification without requiring full-physics simulations, reducing design complexity while preserving the benefits of 3D device structures
Data Source
AI summary
Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.