FinFET Partial Dielectric Isolation for Leakage and Stress Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

FinFET transistors suffer from leakage currents due to lack of effective isolation and stress introduction in the channel region, particularly when using SOI substrates, which limits their performance in aggressively scaled process technology nodes.

Innovation Solution

A partial dielectric isolation technique is employed, where the fin material outside the channel region is removed, and epitaxial growth is used to form source and drain regions on either side of the gate, adding stress to the channel while maintaining isolation from the underlying substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If complete dielectric isolation of the fin is implemented, then leakage currents are reduced, but stress introduction to the channel region is limited

Engineering Contradiction:
Improveleakage currentsVSAvoidstress in channel region
Core Design Contradiction:
Object-generated harmful factorsVSStrength

Solution Approach 1:

The fin structure is segmented into three distinct regions: a first portion extending from the substrate to a first height, a second portion extending from the gate to a second height, and a third portion extending from the gate to a third height. This segmentation allows different portions of the fin to serve different functions - the first portion provides isolation to reduce leakage, while the second and third portions enable stress introduction through epitaxial growth, thereby resolving the contradiction between leakage reduction and stress enhancement.

Inventive Principle:
Principle #1Segmentation

2Strength

If fin material is removed outside channel region, then source-drain regions can contact substrate for stress, but isolation from substrate is compromised

Engineering Contradiction:
Improvestress in channel regionVSAvoidleakage currents
Core Design Contradiction:
StrengthVSObject-generated harmful factors

Solution Approach 1:

Different regions of the fin structure are assigned different properties and functions. The first portion of the fin maintains contact with the substrate to enable stress introduction through epitaxial growth of source and drain regions. The second portion, positioned under the gate, is isolated from the substrate to prevent leakage currents. The third portion extends to enable stress application. This local differentiation of properties allows simultaneous achievement of stress enhancement and leakage reduction.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces leakage currents and introduces stress to the channel region, enhancing the performance of FinFET transistors by isolating the channel from the substrate while allowing source-drain regions to contact the substrate, thus improving control and performance.

Implementation Method 1

epitaxial growth is used to form source and drain regions on either side of the gate

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

a lower (unprotected) portion of the fin (below the lateral barrier layers) is converted to a thermal oxide material which isolates the upper portion of the fin from the underlying substrate material

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS10199392B2FinFET device having a partially dielectric isolated fin structure
Publication Date: 2019.02.05 BELL SEMICONDUCTOR LLC
  • US10199392B2 patent drawing
  • US10199392B2 patent drawing
  • US10199392B2 patent drawing

AI summary

A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.