FinFET Passivation Patterning With In-Chamber By-Product Removal
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in efficiently removing by-products from the etching process, which can lead to defects and reliability issues in semiconductor devices, particularly due to the use of multiple machines and wet etching processes that increase costs and complexity.
Innovation Solution
A single etching machine is used to perform etching, liner removal, and ashing processes within a single etching chamber, employing a 4-in-1 approach that combines these steps to efficiently remove by-products and prevent polymer peeling issues without affecting the properties of the second passivation layer, thereby reducing defects and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple machines and wet etching processes are used to remove by-products, then by-product removal capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines etching, liner removal, and ashing processes into a single integrated tool, eliminating the need for multiple separate machines and wet etching processes. This merging of functions reduces manufacturing complexity while maintaining effective by-product removal capability through a unified plasma-based processing system.
Solution Approach 2:
The integrated tool performs multiple functions (etching, liner removal, and ashing) within a single device, making it a multi-functional system that replaces several specialized machines. This universality reduces the overall manufacturing complexity while preserving all necessary by-product removal capabilities.
2Reliability
If multiple machines are used for etching and liner removal, then process capability is improved, but manufacturing cost increases
Solution Approach 1:
By merging etching, liner removal, and ashing into a single integrated tool, the patent reduces the total number of machines required, thereby lowering capital equipment costs, facility requirements, and operational expenses while maintaining full process capability.
Solution Approach 2:
The multi-functional integrated tool eliminates the need for multiple specialized machines, reducing manufacturing costs through decreased equipment investment, lower maintenance requirements, and simplified facility infrastructure while preserving all necessary process capabilities.
3Reliability
If wet etching processes are used, then by-product removal is improved, but process time and complexity increase
Solution Approach 1:
The patent replaces wet etching (chemical liquid-based process) with plasma-based dry processing. This substitution eliminates the need for separate wet etching and ashing steps, reducing total process time while maintaining effective by-product removal through the plasma chemistry that directly breaks down and removes organic residues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integrated approach reduces defects, eliminates the need for wet cleaning, and enhances the reliability and performance of semiconductor devices by efficiently removing by-products and maintaining the integrity of the second passivation layer, resulting in improved KLA and WAT performance.
Implementation Method 1
The semiconductor substrate and the photoresist are placed into an etching chamber, and the pattern of the photoresist is transferred to the dielectric layer using an etching process
Implementation Method 2
The photoresist is removed prior to removing the photoresist from the etching chamber
Data Source
AI summary
A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.