FinFET Fin Patterning with Etch-Adjusting Layers for Loading Effects

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Solution Overview

Problem

The challenge in forming fin field effect transistors (finFETs) is the loading effect due to etching variations across regions of different pattern density, leading to non-uniform fin widths and etching profiles.

Innovation Solution

The implementation of an etch-adjusting layer between patterning layers and a substrate, combined with selective plasma etching processes, to retard downward etching and enhance lateral etching, ensuring uniform lateral dimensions across regions of varying pattern density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching processes are used without etch-adjusting layers, then the manufacturing process is simpler, but the fin widths become non-uniform across regions of different pattern density

Engineering Contradiction:
Improvefin width uniformityVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

An etch-adjusting layer is introduced as an intermediary between the patterning layer and the substrate. This layer mediates the etching process by providing a controlled interface that compensates for pattern density variations, ensuring uniform fin widths across different regions while maintaining process feasibility

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The etch-adjusting layer is formed in advance before the final fin etching process. This preliminary action pre-compensates for the loading effects that will occur during etching, allowing the subsequent etching process to produce uniform fins without requiring complex real-time adjustments

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If downward etching is not retarded, then the etching process is faster, but the lateral dimensions become non-uniform across different pattern density regions

Engineering Contradiction:
Improvelateral dimension uniformityVSAvoidetching speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The etch-adjusting layer provides different etching characteristics in different regions of the substrate. In dense pattern regions, it retards downward etching more significantly, while in isolated regions, the effect is less pronounced. This local variation in etching behavior ensures uniform lateral dimensions across the entire wafer

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If etching variations are not compensated, then the manufacturing process is simpler, but the fin etching profiles become non-uniform

Engineering Contradiction:
Improveetching profile uniformityVSAvoidprocess simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The etch-adjusting layer serves as a mediator that uniformizes the etching profile across regions with different pattern densities. By providing a consistent interface layer, it enables the formation of uniform fin profiles without requiring complex etching process adjustments

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method achieves consistent fin widths and etching profiles in both dense and isolated regions, enhancing the manufacturing precision and reliability of finFETs.

Implementation Method 1

performing a plasma etching process to form a patterned fin structure

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS20250212497A1Semiconductor device with reduced loading effect
Publication Date: 2025.06.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250212497A1 patent drawing
  • US20250212497A1 patent drawing
  • US20250212497A1 patent drawing

AI summary

The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.