FinFET Pick-Up Region Layout for Higher Latch-Up Immunity
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Solution Overview
Problem
Integrated circuits (ICs) with multigate devices are susceptible to latch-up events due to parasitic structures, which can be triggered by voltage spikes or other events, leading to malfunction or destruction.
Innovation Solution
The IC design includes a pick-up region that continuously extends from one outermost sidewall to the other, increasing its size and reducing resistance, thereby raising the latch-up trigger voltage and enhancing latch-up immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multigate devices are used to increase functional density and reduce feature sizes, then device integration and power consumption are improved, but susceptibility to latch-up events increases due to parasitic structures
Solution Approach 1:
A pick-up region is introduced as an intermediary structure between the n-channel multi-gate device and the p-type semiconductor substrate. This pick-up region acts as a mediator to provide a controlled electrical connection, replacing direct contact that creates parasitic structures. The pick-up region is electrically connected to the n-channel device source/drain region and to a voltage source, creating an intentional conductive path that prevents unwanted parasitic thyristor formation while maintaining device functionality.
Solution Approach 2:
The electrical parameters of the interface between the n-channel multi-gate device and the p-type substrate are changed by introducing the pick-up region with specific doping characteristics and electrical connections. This parameter change transforms the interface from a direct PN junction configuration (which creates parasitic structures) to a controlled multi-layer structure with modified electrical properties, thereby increasing latch-up trigger voltage and improving immunity.
2Reliability
If the pick-up region size is increased to reduce resistance and raise latch-up trigger voltage, then latch-up immunity is improved, but device area increases
Solution Approach 1:
The pick-up region is configured to extend in multiple dimensions, particularly extending laterally between outermost sidewalls of the n-channel multi-gate device. By utilizing the vertical dimension and lateral extension simultaneously, the pick-up region achieves sufficient area to reduce resistance and raise latch-up trigger voltage without proportionally increasing the overall device footprint. The pick-up region's strategic positioning and multi-dimensional extension allow efficient use of available space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved design increases latch-up immunity by reducing the resistance of the pick-up region, making it less susceptible to latch-up events and preventing IC malfunction or destruction.
Implementation Method 1
The pick-up region continuously extends from a first outermost sidewall of the second fin to a second outermost sidewall of the second fin... reducing resistance, thereby raising the latch-up trigger voltage
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.