FinFET Pixel Transistor Layout for Lower Image Noise
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Solution Overview
Problem
Existing imaging elements face challenges in reducing random noise from amplification and selection transistors, leading to deteriorated image quality due to the limitations of conventional methods in reducing pixel noise.
Innovation Solution
The use of multigate transistors, specifically FinFETs, for both selection and amplification transistors in the imaging element, which allows for longer effective channel widths and reduced distance between gate electrodes, thereby minimizing random noise and pixel unit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional transistors are used for selection and amplification transistors, then the pixel unit size can be reduced, but random noise increases and image quality deteriorates
Solution Approach 1:
The patent transitions from planar (2D) transistors to three-dimensional FinFET transistors, utilizing the vertical dimension to create a fin structure. This dimensional change allows the gate to control the channel from three sides, providing better electrostatic control and reducing random noise while maintaining compact pixel unit size.
Solution Approach 2:
The patent changes the effective channel width parameter by using multiple gates in the FinFET structure. The effective channel width is increased relative to the physical footprint, allowing for better signal-to-noise ratio without proportionally increasing the pixel unit area.
2Measurement precision
If conventional planar transistors are used, then manufacturing is simpler, but effective channel width is limited and random noise cannot be reduced
Solution Approach 1:
The patent employs three-dimensional FinFET transistors instead of conventional planar transistors. The vertical fin structure allows the gate to wrap around the channel, providing control from multiple sides and effectively increasing the channel width without proportionally increasing the device footprint.
Solution Approach 2:
The FinFET structure can be viewed as a nested configuration where the gate surrounds the channel from multiple directions, with the vertical fin embedded within the gate structure. This nested arrangement maximizes the effective channel width within a compact footprint.
Data Source
AI summary
An imaging element and device configured for reduced image quality deterioration are disclosed. In one example, a pixel unit of the imaging element includes a selection transistor and an amplification transistor each constituted by a multigate transistor. The selection transistor and amplification transistor may be a FinFET that includes a silicon channel having a fin shape. Moreover, gates of the selection transistor and the amplification transistor may be formed on an identical silicon channel having a fin shape. Furthermore, for example, an ion having a smaller thermal diffusivity than a thermal diffusivity of boron or phosphorous is injected into the silicon channel of the selection transistor. In addition, for example, a work function of a material of a gate electrode of the selection transistor is different from a work function of a material of a gate electrode of the amplification transistor.