FinFET Structure With Planar Source/Drain for Lower Parasitics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fin field-effect transistors (FinFETs) suffer from higher parasitic Miller capacitance and resistance issues, particularly in high-scaled pitch cells like sense amplifiers in memory devices, which hinder performance and increase power consumption.
Innovation Solution
The FinFETs are structured with gate wrapping around fins to maintain channel control and feature planar source and drain regions, reducing Miller capacitance and contact resistance by eliminating inner fringing capacitance and using a continuous, uniform source/drain structure, which also skips an epitaxial process for reduced fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET structure with gate wrapping around fins is used, then channel control is maintained, but parasitic Miller capacitance increases
Solution Approach 1:
The patent extracts and eliminates the source of inner fringing capacitance by removing the gate wrap-around structure that contacts the fin. The gate is terminated before reaching the fin, separating the gate structure from the fin structure to eliminate the parasitic capacitance path while maintaining channel control through alternative means
Solution Approach 2:
The patent introduces an intermediary structure (such as a dummy gate or isolation structure) that maintains the gate-to-channel control function without creating direct contact with the fin that would generate parasitic capacitance. This intermediary allows the gate to control the channel while preventing the harmful capacitive coupling
2Reliability
If conventional FinFET structure is used, then device functionality is achieved, but contact resistance increases
Solution Approach 1:
The patent merges the source/drain regions into a continuous planar structure that extends beneath the fin structure. This merging creates a larger contact area and more uniform current distribution, reducing contact resistance while maintaining proper device functionality through the integrated planar geometry
3Manufacturing precision
If epitaxial process is used for source/drain formation, then doping control is achieved, but fabrication complexity increases
Solution Approach 1:
The patent skips the separate epitaxial growth step for source/drain formation by using alternative doping methods such as ion implantation or in-situ doping during subsequent processing steps. This allows doping control to be achieved through precise implantation techniques while reducing the overall fabrication process complexity and step count
Data Source
AI summary
A variety of applications can include apparatus having a fin field-effect transistor with a gate wrapping around fins to maintain good channel control and planar source and drain regions to reduce Miller capacitance and contact resistance. The reduced parasitic capacitance and resistance can be translated into higher performance and lower power. A fin field-effect transistor can include a bulk semiconductor region having a planar source region structured as a first top portion of the bulk semiconductor region and a planar drain region structured as a second top portion of the bulk semiconductor region, with one or more semiconductor fins contacting the planar source region and the planar drain region with a gate wrapped around the one or more semiconductor fins.