FinFET Source/Drain Plasma Doping for Low Contact Resistance
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Solution Overview
Problem
Existing techniques for manufacturing FinFETs face challenges in reducing source/drain contact resistance, particularly due to dopant tailing and threshold voltage shifts caused by ion implantation, which limits the effectiveness of increased doping and introduces short-channel effects.
Innovation Solution
The use of a plasma doping (PLAD) process and a spacer deposition-etch process to prevent dopant loss, combined with the use of indium as a P-type dopant for NMOS devices, which allows simultaneous doping of N-type and P-type regions without additional masking, providing an abrupt doping profile and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation doping is used to reduce source/drain contact resistance, then contact resistance decreases, but dopant tailing occurs causing threshold voltage shift and short-channel effects
Solution Approach 1:
The patent changes the doping method from ion implantation to plasma doping (PLAD), altering the physical and chemical parameters of the doping process. PLAD achieves higher dopant concentration with abrupt profiles by using plasma chemistry rather than ion bombardment, thereby reducing contact resistance while preventing dopant tailing and threshold voltage shifts
Solution Approach 2:
The patent replaces the mechanical ion implantation process with a plasma-based chemical doping process. Instead of physically implanting ions into the semiconductor lattice, PLAD uses plasma-enhanced chemical reactions to deposit dopants, eliminating the mechanical damage and tailing effects associated with ion implantation
2Reliability
If increased source/drain doping is used to reduce contact resistance, then contact resistance decreases, but short-channel effects are induced
Solution Approach 1:
The patent changes the doping profile characteristics by using PLAD instead of ion implantation. The plasma doping process achieves extremely abrupt doping profiles with peak concentrations at the surface, preventing the gradual dopant distribution that causes short-channel effects while maintaining low contact resistance through high surface dopant concentration
3Ease of manufacture
If conventional doping processes are used for both NMOS and PMOS regions, then doping can be performed, but additional masking steps are required
Solution Approach 1:
The patent uses indium as a universal dopant that can dope both NMOS and PMOS regions effectively. Indium serves multiple functions: it acts as a P-type dopant for PMOS and can also be used in NMOS regions, eliminating the need for separate doping processes and masking steps for different device types, thereby simplifying the manufacturing process
4Manufacturing precision
If Ge amorphization process is used prior to doping, then doping profile control improves, but process complexity and time increase
Solution Approach 1:
The patent extracts and eliminates the Ge amorphization process step from the conventional doping sequence. By using plasma doping, the patent achieves excellent doping profile control without requiring the preliminary amorphization step, thereby reducing process complexity and manufacturing time while maintaining or improving doping precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 10-20% reduction in contact resistance compared to conventional methods, eliminating the need for a separate Ge amorphization process and preventing threshold voltage shifts, while maintaining gate control and mitigating short-channel effects.
Implementation Method 1
the use of a plasma doping (PLAD) process and a spacer deposition-etch process to prevent dopant loss
Implementation Method 2
a spacer deposition-etch process to prevent dopant loss
Implementation Method 3
the use of indium as a P-type dopant for NMOS devices, which allows simultaneous doping of N-type and P-type regions
Data Source
AI summary
A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.