FinFET PLL Clock Synchronization Without LC Oscillator Coupling
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Solution Overview
Problem
Existing clock generation systems for wireless communications face challenges with high precision synchronization, particularly due to electro-magnetic coupling between inductor-based oscillators, reduced production yield from non-scaling inductors, and unwanted cross-talk from integrating numerous PLLs based on LC oscillators synchronized to external references.
Innovation Solution
The use of FinFET oscillators in a closed loop configuration, which generates high precision synchronization clock signals without the need for on-chip inductor-based oscillators, thereby avoiding latch up problems and magnetic and capacitive coupling issues, and includes a phased-lock loop (PLL) with components like a time-to-digital converter, loop filter, digital-to-time converter, and multi-modulus divider to generate clock signals in the range of 20-30 GHz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If on-chip LC oscillators are used for clock generation, then synchronization precision can be improved, but electro-magnetic coupling and cross-talk between oscillators occur
Solution Approach 1:
The patent extracts and removes the inductor component from the oscillator design, transitioning from an LC oscillator to a ring oscillator implementation. This eliminates the source of electro-magnetic coupling and cross-talk while maintaining the clock generation and synchronization functions.
Solution Approach 2:
The patent replaces the physical inductor-based LC oscillator system with a purely electronic ring oscillator system using transistors and capacitors. This substitution eliminates the magnetic field generation inherent in inductors while achieving the same frequency generation purpose through electronic means.
2Productivity
If inductor-based oscillators are used, then clock signals can be generated, but production yield is reduced due to non-scaling inductors
Solution Approach 1:
The patent changes the fundamental parameters of the oscillator design by removing the inductor component entirely and using only standard CMOS process-compatible elements (transistors and capacitors). This enables the design to scale with standard semiconductor manufacturing processes, improving production yield.
Solution Approach 2:
The patent uses standard, readily available CMOS process elements instead of specialized inductor structures that require non-standard fabrication. This approach uses common, well-understood process elements that can be manufactured at scale with high yield.
3Measurement precision
If multiple PLLs based on LC oscillators are integrated, then high precision synchronization is achieved, but unwanted cross-talk increases
Solution Approach 1:
The patent removes the inductor element that causes cross-talk, replacing LC oscillators with ring oscillators in each PLL. This extraction of the problematic component allows multiple PLLs to be integrated closely without the electro-magnetic interference that would otherwise occur between them.
Solution Approach 2:
The patent enables the merging of multiple PLL functions onto a single chip by eliminating the cross-talk issue through the use of ring oscillators. This allows dense integration of multiple synchronization circuits that would otherwise be too noisy to coexist.
Data Source
AI summary
A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.