FinFET Dummy PODE Structures for Leakage Control
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Solution Overview
Problem
In integrated circuits interfacing high and low voltage domains, low voltage devices are susceptible to high voltage violations due to uncontrolled leakage currents, leading to potential damage and reliability issues, especially when high voltage devices operate with supply voltages exceeding the maximum voltage rating of low voltage devices.
Innovation Solution
The implementation of n-type finFET transistors with polysilicon on OD edge (PODE) structures, where these structures are tied to the P-well to limit leakage currents by maintaining their voltage potential with the P-well, thereby preventing excessive voltage exposure to low voltage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high voltage devices are integrated with low voltage devices in the same circuit, then circuit functionality and integration density are improved, but low voltage devices are exposed to high voltage violations due to uncontrolled leakage currents
Solution Approach 1:
The PODE structures serve as intermediary elements between the high voltage drain region and the P-well. By introducing these dummy polysilicon structures that are electrically connected to the P-well, the patent creates a controlled path for leakage currents, preventing them from causing uncontrolled voltage rises that would damage low voltage devices.
Solution Approach 2:
The PODE structures are formed during the manufacturing process before the circuit operates. These structures are pre-configured with electrical connections to the P-well, establishing a protective mechanism against leakage currents before any high voltage operation occurs, thereby preventing potential damage to low voltage devices.
2Reliability
If polysilicon structures are added to the finFET device, then leakage current control is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The PODE structures are merged with the existing gate polysilicon layer formation process. By combining the creation of gate polysilicon and PODE structures into a single manufacturing step, the patent adds the necessary leakage control functionality without proportionally increasing manufacturing complexity.
Solution Approach 2:
The polysilicon material serves multiple functions: it forms the gate structure for controlling the finFET channel and simultaneously creates the PODE structures for leakage current control. This multi-functionality reduces the need for additional specialized materials and processing steps.
Data Source
AI summary
A circuit includes a plurality of voltage supply terminals including a lowest voltage supply terminal, an N-type finFET, and a current path electrically coupled to the lowest voltage supply terminal, where the N-type finFET transistor is located in the current path. The N-type finFET transistor includes at least one semiconductor fin, a gate structure made of a gate material located over the at least one fin, an end structure of the gate material located over an end of the at least one fin, a source electrode, and a drain electrode. The at least one fin is located over a well region, and the end structure is electrically tied to the well region, in which the well region is not electrically tied to the lowest voltage supply terminal.