FinFET Standard Cell Polysilicon Dummy Verification
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Solution Overview
Problem
The use of finFET transistors in standard cell methodologies for integrated circuits complicates layout versus schematic verification due to the inaccurate modeling of polysilicon structures, leading to parasitic capacitance and leakage current issues, which are not accurately predicted by conventional pre- and post-layout simulations.
Innovation Solution
Incorporating recognition layers in the standard cell definitions to model polysilicon on OD edge (PODE) structures as three-terminal devices and parasitic resistors, ensuring accurate representation in both pre- and post-layout simulations, thereby enabling correct layout versus schematic comparison without modifying existing design tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If finFET transistors are used in standard cell methodologies, then device performance and density are improved, but layout versus schematic verification accuracy deteriorates due to inaccurate modeling of polysilicon structures
Solution Approach 1:
The polysilicon structure is segmented into multiple regions (gate polysilicon and cell edge polysilicon) with distinct modeling approaches. The gate polysilicon is modeled as a three-terminal device with parasitic capacitance, while the cell edge polysilicon is modeled as a two-terminal device with leakage current, allowing each segment to be verified independently and accurately.
Solution Approach 2:
Different modeling characteristics are applied to different locations of the polysilicon structure. The gate region uses three-terminal device modeling with capacitance for accurate electrical characterization, while the cell edge regions use two-terminal device modeling with leakage current for accurate parasitic effects, ensuring local verification accuracy matches the specific functional requirements.
2Ease of operation
If conventional pre- and post-layout simulations are used, then design verification is simplified, but timing simulation accuracy deteriorates due to parasitic capacitance and leakage current issues
Solution Approach 1:
The patent introduces intermediate verification models (three-terminal devices for gate polysilicon and two-terminal devices for cell edge polysilicon) that act as mediators between the layout geometry and the electrical characteristics. These intermediate models enable accurate timing simulation by properly accounting for parasitic capacitance and leakage current without requiring complex modifications to existing verification tools.
3Reliability
If polysilicon dummy structures are added to standard cells, then manufacturing process protection is improved, but layout verification complexity increases due to additional structures
Solution Approach 1:
The cell edge polysilicon structures are extracted as separate verification elements from the main transistor structure. By treating these dummy structures as independent two-terminal devices with leakage current, the verification process can handle them separately using simplified models, reducing the overall verification complexity while maintaining accurate representation of their protective function.
Data Source
AI summary
Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.