FinFET Power Optimization via Non-Critical Path Fin Adjustment
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Solution Overview
Problem
Conventional FinFET transistors face challenges in power optimization, leading to high power consumption that affects battery life and circuit performance, especially when scaling down to smaller sizes.
Innovation Solution
A method is introduced to categorize fin-based semiconductor devices into critical and non-critical paths in the FinFET design, where adjustments such as reducing the number, increasing the width, or modifying the electrical connections of fins on non-critical paths are made to optimize power consumption, resulting in a refined FinFET design with lower current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET design is used to replace planar MOS transistor for scaling down, then device performance and integration density are improved, but power consumption increases
Solution Approach 1:
The patent segments the FinFET devices into two categories: critical path devices and non-critical path devices. This segmentation allows differential treatment where non-critical path devices can be optimized for lower power consumption by adjusting fin parameters, while critical path devices maintain original specifications for performance. The segmentation resolves the contradiction by enabling power optimization without compromising overall circuit performance.
Solution Approach 2:
The patent applies local quality by implementing different fin configurations in different locations within the circuit. Specifically, non-critical path FinFETs use modified fin parameters (reduced width, height, or number of fins) to lower power consumption, while critical path FinFETs maintain original high-performance specifications. This localized differentiation resolves the power-performance contradiction by optimizing each region according to its functional requirements.
2Use of energy by moving object
If the number of fins is increased to reduce current and optimize power, then power consumption decreases, but device complexity increases
Solution Approach 1:
The patent applies partial action by selectively modifying only non-critical path FinFETs rather than all devices in the circuit. The optimization is partial in that it targets specific devices where power reduction is acceptable without impacting overall circuit performance. This resolves the contradiction by achieving power optimization through selective modification rather than universal complexity increase.
Data Source
AI summary
A method of designing a fin-based transistor for power optimization includes following steps. A planar field-effect transistor (planar-FET) design including a plurality of planar semiconductor devices is received. An initial fin field-effect transistor (FinFET) design including a plurality of fin-based semiconductor devices corresponding to the planar semiconductor devices is generated. A timing analysis is performed to the initial FinFET design to recognize at least a critical path and at least a non-critical path in the initial FinFET design. The non-critical path includes at least one of the fin-based semiconductor devices. The fin-based semiconductor device on the non-critical path is adjusted and thus a refined FinFET design is generated. A current required by the refined FinFET design is lower than a current required by the initial FinFET design.