FinFET Punch-Through Prevention via Ion Implantation
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Solution Overview
Problem
The Fin FET manufacturing process faces challenges in ensuring stable performance due to the difficulty in preventing punch-through phenomena at the bottom portions of the source and drain regions, leading to leakage currents as device dimensions decrease.
Innovation Solution
A method involving punch-through preventing ion implantation, followed by an annealing process, and the formation of insulating structures with diffusion preventing ions to restrain ion diffusion and create threshold voltage adjusting layers, ensuring the ions primarily remain within their respective fin portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed to prevent punch-through phenomena, then transistor leakage current is reduced, but ion diffusion during subsequent processes causes dose loss and reduces manufacturing precision
Solution Approach 1:
The patent performs ion implantation to form the punch-through preventing layer before the fin formation etching process. This preliminary action ensures that ions are implanted into the substrate at controlled locations before any etching occurs, preventing ion diffusion into unwanted areas and maintaining precise ion concentration control while effectively preventing punch-through phenomena
Solution Approach 2:
The patent creates a punch-through preventing layer with specific ion concentration and depth characteristics tailored for each region (NMOS and PMOS). By controlling the implantation parameters (ion type, energy, dose) and using selective etching to expose different depths, the patent achieves locally optimized ion distribution that prevents punch-through while maintaining manufacturing precision
2Productivity
If etching is performed to form fin portions, then device integration is improved, but the etching process may remove implanted ions and reduce the effectiveness of punch-through prevention
Solution Approach 1:
The patent performs ion implantation before fin formation etching to ensure ions are already in place. The etching process then selectively removes material to form fins while leaving the implanted ions in the substrate, preventing punch-through phenomena. This sequence ensures both high device integration and effective punch-through prevention
Solution Approach 2:
The patent segments the substrate into different regions (NMOS and PMOS) with different ion implantation parameters and etching depths. This segmentation allows each region to have optimized punch-through prevention while maintaining overall device integration and functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents punch-through phenomena, enhances the performance of semiconductor structures, and increases manufacturing yield by maintaining ion concentration and reducing diffusion-related dose loss.
Implementation Method 1
performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer
Implementation Method 2
implanting first punch-through preventing ions into the NMOS region of the substrate to form a first implantation layer; implanting second punch-through preventing ions into the PMOS region of the substrate to form a second implantation layer
Implementation Method 3
performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer
Data Source
AI summary
In various embodiments of the disclosed subject matter, a semiconductor structure, and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: providing a substrate; implanting first punch-through preventing ions into an NMOS region of the substrate to form a first implantation layer; implanting second punch-through preventing ions into a PMOS region of the substrate to form a second implantation layer; etching the substrate to form first fin portions in the NMOS region, and second fin portions in the PMOS region, the remaining first implantation layer forms a first punch-through preventing layer, the remaining second implantation layer forms a second punch-through preventing layer; forming insulating structures between adjacent first fin portions and second fin portions; and performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer.