FinFET P-Well Co-Implantation to Limit Dopant Diffusion
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Solution Overview
Problem
The challenge in FinFET manufacturing is the diffusion of dopants during thermal processes, leading to dopant loss and increased resistivity, which can cause latch-up issues in CMOS devices due to inter-diffusion between p-well and n-well regions and diffusion into isolation materials.
Innovation Solution
Co-implantation of a diffusion-retarding element like carbon with p-type dopants in FinFETs to form co-implantation regions that reduce dopant diffusion, specifically using tilt implantation to control the depth and extent of carbon distribution, thereby minimizing dopant loss and inter-diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal processes are used during FinFET manufacturing, then dopant diffusion occurs which can activate dopants and form necessary doping profiles, but dopant loss and increased resistivity occur leading to latch-up issues
Solution Approach 1:
A co-implantation region is introduced as an intermediary layer between the well region and isolation regions. This co-implantation region acts as a diffusion barrier that prevents dopant diffusion into isolation regions while allowing the well region to maintain its dopant concentration. The co-implantation region is formed by implanting ions at a different angle and energy level, creating a distinct layer that blocks harmful dopant migration during thermal processes.
Solution Approach 2:
The co-implantation region is formed in advance before final doping steps. By pre-forming this protective layer at a shallower depth with specific ion implantation parameters, the structure is prepared to resist dopant diffusion during subsequent thermal annealing processes. This preliminary action ensures that when thermal processes occur later, the dopant concentration in well regions is preserved and latch-up is prevented.
2Manufacturing precision
If standard ion implantation is used to form well regions, then dopant distribution can be controlled, but dopant loss occurs during subsequent thermal processes increasing resistivity
Solution Approach 1:
The co-implantation region serves as a protective intermediary that reduces dopant loss during thermal processes. By implanting ions at a shallower depth and different angle, a barrier layer is created that prevents dopant atoms from migrating out of the well region during annealing, thereby maintaining dopant concentration and reducing resistivity increases.
Solution Approach 2:
Different ion implantation parameters are used for the co-implantation region compared to standard well region doping. The co-implantation uses lower energy and different angular parameters to create a shallow barrier layer, while subsequent well doping uses higher energy to reach deeper depths. This parameter differentiation creates a layered structure that preserves dopant concentration while maintaining precise dopant distribution control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The co-implantation process effectively reduces dopant diffusion into isolation regions, maintains dopant concentration in FinFETs, and decreases the likelihood of latch-up, thereby enhancing the performance and reliability of FinFETs.
Implementation Method 1
performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region
Implementation Method 2
The co-implantation process effectively reduces dopant diffusion into isolation regions, maintains dopant concentration in FinFETs
Data Source
AI summary
A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the deep p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.