FinFET Recess Cleaning Sequence for Source/Drain Epitaxy
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Solution Overview
Problem
Existing FinFET device fabrication methods struggle to effectively clean the recesses in the fin of FinFET devices, leading to impurities and oxide layers that can adversely affect the formation of source/drain regions and device performance.
Innovation Solution
A three-step cleaning method involving a plasma cleaning step using hydrogen radicals and atomic hydrogen, followed by a wet etch step and a dry etch step, is employed to remove impurities and adjust the profile of the recesses in FinFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cleaning methods are used for recesses in FinFET fins, then the fabrication process is simple, but impurities and oxide layers remain that adversely affect source/drain region formation and device performance
Solution Approach 1:
The cleaning process is divided into three distinct sequential steps: plasma cleaning to remove organic contaminants, wet etching to remove oxide layers, and dry etching to perform final cleaning. This segmentation allows each step to target specific types of impurities, achieving thorough cleaning without requiring overly aggressive single-step processes that could damage the fin structure.
Solution Approach 2:
The plasma cleaning step is performed first as a preliminary action to remove organic contaminants and prepare the surface before the wet etching step. This preliminary cleaning prevents organic impurities from interfering with subsequent wet etching of oxide layers, ensuring that each step works optimally on its target contaminant type.
2Manufacturing precision
If aggressive cleaning methods are used to remove all impurities, then cleaning effectiveness improves, but damage to the fin structure and gate spacers may occur
Solution Approach 1:
The cleaning process applies different cleaning mechanisms to different locations and contaminant types: plasma cleaning targets organic contaminants on exposed fin surfaces, wet etching targets oxide layers, and dry etching provides final precision cleaning. This localized approach ensures thorough removal of all contaminant types while maintaining fin structure integrity through controlled, selective cleaning actions.
Solution Approach 2:
The process uses controlled changes in cleaning parameters including plasma power, etch chemistry composition, and process duration to optimize cleaning effectiveness. By carefully adjusting these parameters, the process achieves thorough contaminant removal while preventing excessive etching that could damage the fin structure or gate spacers.
3Reliability
If the recess profile is not adjusted, then the fabrication process is straightforward, but contact resistance and drain induced barrier lowering cannot be optimized
Solution Approach 1:
The plasma cleaning step serves a dual function: it cleans organic contaminants from the fin surface and simultaneously performs preliminary profile adjustment by removing portions of the exposed fin. This preliminary profile modification prepares the recess geometry for optimal source/drain epitaxial growth, enabling better electrical performance before the main epitaxial formation step.
Solution Approach 2:
The plasma cleaning process performs multiple functions simultaneously: removing organic contaminants, adjusting the recess profile, and preparing the surface for subsequent epitaxial growth. This multi-functionality consolidates what could be separate process steps into one operation, maintaining ease of manufacture while achieving the electrical performance benefits of profile control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This cleaning method effectively removes impurities and oxide layers, allowing for better epitaxial growth of source/drain regions, reduced contact resistance, and improved control over drain induced barrier lowering (DIBL) and channel resistance.
Implementation Method 1
a plasma cleaning step using hydrogen radicals and atomic hydrogen
Implementation Method 2
using hydrogen radicals and atomic hydrogen
Implementation Method 3
a wet etch step
Implementation Method 4
a dry etch step
Data Source
AI summary
In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.