FinFET Source/Drain Recess Cleaning for Contact Landing Control
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Solution Overview
Problem
Existing FinFET devices face challenges in achieving optimal device performance due to limitations in surface quality and control of the source/drain recess, which affect the contact landing process and device performance.
Innovation Solution
The method involves sequentially wet cleaning, plasma treating, and subsequent wet cleaning of the source/drain recess to enlarge its width, resulting in an arc-shape surface profile and improved surface quality, allowing for better control of the distance between the source/drain epitaxial structure and the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used for FinFET devices, then manufacturing process is simpler, but device performance is insufficient due to poor surface quality and limited control of source/drain recess
Solution Approach 1:
The fabrication process is segmented into multiple distinct stages: forming gate structures, forming spacers, selectively removing spacers, forming source/drain recesses, and selective epitaxial growth. Each stage addresses specific requirements independently, allowing optimization of surface quality and recess control without overwhelming complexity in a single step.
Solution Approach 2:
Gate structures and spacers are formed in advance before creating source/drain recesses. The spacers serve as preliminary structures that define the boundaries and dimensions of the recesses, enabling precise control of recess width and position before the actual recess formation and epitaxial growth occur.
2Manufacturing precision
If source/drain recess width is increased to improve contact landing, then manufacturing precision is improved, but device structure becomes more complex
Solution Approach 1:
The spacer structures serve as intermediary elements that mediate between the gate structures and the source/drain recesses. By controlling spacer dimensions and selectively removing portions, the recess width is precisely controlled without requiring direct complex patterning of the recess boundaries, simplifying the overall process while maintaining high precision.
Solution Approach 2:
The width of source/drain recesses is controlled by changing the dimensions and removal extent of spacer structures. By adjusting spacer thickness, material composition, and removal parameters, the recess width is precisely tuned to optimize contact landing precision without increasing overall device structural complexity.
3Manufacturing precision
If multiple cleaning and treatment steps are applied to source/drain recess, then surface quality is improved, but manufacturing time increases
Solution Approach 1:
Wet cleaning and plasma treatment are performed on source/drain recesses before epitaxial growth to pre-condition the surfaces. This preliminary surface preparation ensures optimal surface quality and cleanliness, enabling high-quality epitaxial layer formation in a single growth step, thereby reducing total fabrication time despite multiple treatment steps.
Solution Approach 2:
The cleaning and treatment steps are performed in sequence without interruption to the overall fabrication flow. Wet cleaning removes contaminants, plasma treatment activates and further cleans surfaces, and immediately subsequent epitaxial growth utilizes the prepared surfaces. This continuous sequence minimizes idle time and maintains momentum in the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by enlarging the process window for contact landing, improving surface quality, and reducing the short channel effect, thereby increasing yield and device reliability.
Implementation Method 1
treating the source/drain recess with a plasma process
Data Source
AI summary
A method for forming a semiconductor structure includes forming a gate structure over a substrate. The method also includes forming a spacer on a sidewall of the gate structure. The method also includes forming a source/drain recess beside the spacer. The method also includes treating the source/drain recess and partially removing the spacers in a first cleaning process. The method also includes treating the source/drain recess with a plasma process after performing the first cleaning process. The method also includes treating the source/drain recess in a second cleaning process after treating the source/drain recess with the plasma process. The method also includes forming a source/drain structure in the source/drain recess after performing the second cleaning process.


