FinFET Source/Drain Recess Cleaning for Crystal Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As the minimum feature sizes in semiconductor devices are reduced, challenges arise in forming recesses for epitaxial source/drain regions in FinFET devices, including contamination removal and reshaping of recesses to improve device performance.

Innovation Solution

A plasma cleaning process using hydrogen radicals is employed to remove contamination from the recess surfaces and reshape them, resulting in epitaxial source/drain regions with improved crystalline plane alignment and reduced dopant diffusion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching processes are used to form recesses, then the recesses can be formed, but contamination remains on the recess surfaces and the crystalline plane alignment is poor

Engineering Contradiction:
Improvecrystalline plane alignmentVSAvoidcontamination
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent changes the chemical parameters of the etching process by using a plasma-based etching process with specific gas compositions (CHF3, CF4, or SF6) and controlled process conditions. This parameter change enables both effective contamination removal and precise crystalline plane alignment in the formed recesses, resolving the contradiction between manufacturing precision and harmful factors.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces conventional mechanical or chemical etching methods with a plasma-based etching process. The plasma process uses ion bombardment and chemical reactions to achieve superior surface cleaning and crystalline plane alignment, substituting the conventional approach with a more advanced physical-chemical process that simultaneously addresses both contamination and alignment issues.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but additional fabrication challenges and contamination issues arise

Engineering Contradiction:
Improveintegration densityVSAvoidfabrication challenges
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent adjusts the etching process parameters including gas flow rates, pressure, and power levels to optimize the formation of smaller recesses with reduced feature sizes. By carefully controlling these parameters, the process maintains high precision and cleanliness even at smaller dimensions, enabling increased integration density without proportionally increasing fabrication challenges.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The plasma cleaning process enhances the performance of FinFET devices by reducing electrical resistance, minimizing defects, and increasing on-state current, while also reducing unwanted dopant diffusion and leakage effects.

Implementation Method 1

A plasma cleaning process using hydrogen radicals is employed to remove contamination from the recess surfaces

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

The plasma cleaning process using hydrogen radicals is employed to remove contamination from the recess surfaces and reshape them

Methodology Applied
Scientific EffectHydrogen radicals:

Implementation Method 3

heating the holder to a process temperature between 300° C. and 1000° C.

Methodology Applied
Scientific EffectHeating: Heating

Data Source

PatentUS20250126821A1FINFET Device and Method of Forming Same
Publication Date: 2025.04.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250126821A1 patent drawing
  • US20250126821A1 patent drawing
  • US20250126821A1 patent drawing

AI summary

A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.