FinFET Source/Drain Recess Depth Tuning for Resistance Balance
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Solution Overview
Problem
As transistor sizes shrink, manufacturing processes become increasingly complex to improve production yield and device performance, particularly in reducing resistance while maintaining compact size, especially in FinFETs where existing methods fail to balance channel resistance and contact resistance effectively.
Innovation Solution
The method involves forming n-type and p-type FinFETs with recessed source/drain regions, where the depth of the n-type source/drain contact recess is greater than that of the p-type, allowing for a better balance between channel and contact resistance, and using epitaxy layers with varying doping concentrations and germanium content to optimize resistance and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the transistor size is reduced to improve device integration, then the device area decreases, but the resistance of source/drain contact plugs increases and manufacturing complexity increases
Solution Approach 1:
The patent applies different etch depths for n-type and p-type source/drain contact recesses, creating locally optimized contact structures. The n-type recess has a first depth while the p-type recess has a second depth, allowing each contact type to achieve optimal electrical properties for its specific requirements, thereby reducing overall contact resistance despite miniaturization
Solution Approach 2:
The patent changes the depth parameter of contact recesses differently for n-type and p-type devices. By adjusting the etch depth parameter independently for each contact type, the invention optimizes the contact resistance parameter for each, solving the resistance increase problem that occurs during transistor size reduction
2Area of moving object
If the transistor size is reduced to improve device integration, then the device area decreases, but the manufacturing process complexity increases
Solution Approach 1:
The patent introduces localized variations in contact recess depth for different contact types (n-type vs p-type) while maintaining a unified overall process flow. This local differentiation achieves optimal electrical properties without requiring completely separate manufacturing processes, thereby limiting the increase in manufacturing complexity
Solution Approach 2:
The patent segments the contact formation process into distinct depth control steps for n-type and p-type contacts. By dividing the etching process into selective depth stages, the invention manages complexity through structured process segmentation rather than attempting to handle all contacts uniformly
3Ease of manufacture
If existing methods are used for FinFET contact formation, then the process is simpler, but the balance between channel resistance and contact resistance is poor
Solution Approach 1:
The patent applies different etch depths for n-type and p-type source/drain contact recesses, creating locally optimized contact structures. The n-type recess has a first depth while the p-type recess has a second depth, allowing each contact type to achieve optimal electrical properties for its specific requirements, thereby reducing overall contact resistance despite miniaturization
Solution Approach 2:
The patent changes the depth parameter of contact recesses differently for n-type and p-type devices. By adjusting the etch depth parameter independently for each contact type, the invention optimizes the contact resistance parameter for each, solving the resistance increase problem that occurs during transistor size reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overall resistance in FinFETs, particularly for p-type devices, improving their performance by balancing channel and contact resistance, and maintaining low contact resistance in n-type FinFETs, thus enhancing the overall performance of advanced transistors.
Implementation Method 1
using epitaxy layers with varying doping concentrations and germanium content to optimize resistance and performance
Data Source
AI summary
A method includes forming an n-type Fin-Field Effect Transistor (FinFET) and a p-type FinFET. The forming of the n-type FinFFT includes: forming a first auxiliary gate stack over a first semiconductor fin; forming an n-type source/drain region on the first semiconductor fin adjacent to the first auxiliary gate stack; and performing a first etch to form a first recess with a first depth on a first top surface of the n-type source/drain region. The forming of the p-type FinFFT includes: forming a second auxiliary gate stack over a second semiconductor fin; forming a p-type source/drain region on the second semiconductor fin adjacent to the second auxiliary gate stack; and performing a second etch to form a second recess with a second depth on a second top surface of the p-type source/drain region. The first depth is greater than the second depth.