FinFET Source/Drain Recess Shaping for Dopant Diffusion Control

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Solution Overview

Problem

As semiconductor devices, such as FinFETs, continue to shrink in feature size, controlling the shape of epitaxial source/drain regions to improve performance becomes challenging due to increased dopant diffusion and leakage issues, particularly with the existing etching processes that do not effectively manage crystalline plane orientations.

Innovation Solution

The method involves reshaping recesses between fins using hydrogen radicals in a plasma etching process, selectively etching crystalline planes to create a pointed or V-shaped bottom, which reduces dopant diffusion and enhances the shape of epitaxial source/drain regions, thereby improving FinFET performance by increasing the bottom proximity and reducing Drain-Induced Barrier Lowering (DIBL) effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional etching processes are used to form recesses between fins, then the manufacturing process is simpler, but dopant diffusion and leakage increase, degrading device performance

Engineering Contradiction:
Improvedevice performanceVSAvoidetching process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The etching process is divided into two distinct stages: a first etching process that forms initial recesses between fins, and a second etching process that selectively sharpens the bottom corners of these recesses. This segmentation allows each process to be optimized for its specific function, with the second process targeting only the critical bottom corner regions to reduce dopant diffusion without requiring complete process redesign

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second etching process applies selective removal specifically at the bottom corners of the recesses where dopant diffusion is most problematic, rather than uniformly etching the entire recess. This localized approach sharpens the critical regions to improve device performance while maintaining the overall recess structure and minimizing additional process complexity

Inventive Principle:
Principle #3Local quality

2Productivity

If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but controlling the shape of epitaxial source/drain regions becomes more difficult due to increased dopant diffusion

Engineering Contradiction:
Improveintegration densityVSAvoidshape control of epitaxial source/drain regions
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The second etching process is performed before epitaxial growth of source/drain regions, preliminarily shaping the recess bottom corners to a sharper geometry. This preliminary action prevents dopant diffusion issues during subsequent epitaxial growth, enabling better shape control even at reduced feature sizes and maintaining manufacturing precision as integration density increases

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces dopant diffusion and leakage, enhancing the performance of FinFETs by controlling the shape of epitaxial source/drain regions, leading to improved device speed and current uniformity.

Implementation Method 1

reshaping the first recess to form a reshaped first recess using a second etching process

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 2

The second etching process selectively etches crystalline planes having a first orientation relative to second crystalline planes having a second orientation

Methodology Applied
Scientific EffectSelective etching of crystalline planes:

Implementation Method 3

epitaxially growing a source/drain region in the reshaped first recess

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20230377991A1FinFET Device and Method of Forming Same
Publication Date: 2023.11.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230377991A1 patent drawing
  • US20230377991A1 patent drawing
  • US20230377991A1 patent drawing

AI summary

A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.