FinFET Source/Drain Recess Etching for Uniform Channel Resistance
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, maintaining constant channel resistance from top to bottom in FinFET devices becomes challenging due to non-uniform source/drain region proximity, leading to uneven resistance and current flow issues.
Innovation Solution
A multi-step etching process combining anisotropic and isotropic etching techniques is employed to form recesses for epitaxial source/drain regions, ensuring uniform proximity and consistent channel resistance across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-step etching is used to form source/drain regions, then the manufacturing process is simple, but the source/drain region proximity is non-uniform leading to uneven channel resistance
Solution Approach 1:
The etching process is divided into multiple sequential steps (first etch step, second etch step, third etch step) with different etching conditions and selectivities. Each step targets specific depth ranges and materials, allowing precise control over source/drain region formation and uniform proximity achievement
Solution Approach 2:
The patent varies etching parameters including gas composition (CHF3, CF4, SF6, Cl2, BCl3), power levels (50-3000W), pressure (2-80 mTorr), and temperature (25-100°C) across different etching steps to achieve selective removal of materials and control etching anisotropy, thereby achieving uniform source/drain region proximity
2Manufacturing precision
If feature sizes are reduced to increase integration density, then more components can be integrated, but maintaining constant channel resistance becomes more difficult
Solution Approach 1:
The patent applies different etching conditions to different regions and depths of the substrate. The first etch step uses high power for rapid removal, while subsequent steps use lower power with different gas compositions for precise control. This localized control of etching parameters ensures uniform source/drain proximity even at reduced feature sizes
Solution Approach 2:
The patent performs preliminary etching steps that create intermediate structures and profiles before final source/drain region formation. The first etch step creates an initial profile, followed by second and third steps that refine the structure, ensuring that when miniaturization occurs, the channel resistance remains uniform due to the pre-established geometric control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves uniform source/drain region proximity and maintains constant channel resistance from top to bottom, improving the performance and reliability of FinFET devices by optimizing the etching process.
Implementation Method 1
performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process
Implementation Method 2
The isotropic etching process may be performed with an etchant being pushed toward a deeper level of the substrate
Data Source
AI summary
A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.