FinFET Source/Drain Recess Layout for Multi-Device PPAC Scaling
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Solution Overview
Problem
Existing semiconductor manufacturing techniques struggle to simultaneously optimize the performance and design requirements of highly scaled system-on-a-chip (SOC) devices, high-performance computing (HPC) devices, and input/output (IO) devices to meet power, performance, area, and cost (PPAC) scaling requirements, as each device type has distinct design and performance needs.
Innovation Solution
The method involves using multiple photolithography and etch steps to independently optimize the source/drain proximity and depth for each device type, employing a two-step photo/etch process (2P2E) or more for N-type and P-type source/drain regions, allowing for co-optimization of SOC, HPC, and IO devices, while maintaining performance and reliability across different device types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single manufacturing process is used for all device types, then manufacturing simplicity is maintained, but the ability to optimize each device type's specific performance requirements is lost
Solution Approach 1:
The manufacturing process is divided into separate photolithography and etch steps for different device regions. SOC devices, HPC devices, and IO devices each receive customized processing sequences, allowing independent optimization of source/drain proximity and depth for each device type while maintaining overall process integration
Solution Approach 2:
Different source/drain structures are created for different device types within the same semiconductor device. SOC devices receive one configuration, HPC devices receive another, and IO devices receive a third, with each locally optimized for its specific performance requirements through region-specific photolithography and etch parameters
2Speed
If source/drain proximity is reduced to improve device speed, then HPC device performance is enhanced, but SOC device reliability and IO device breakdown protection are compromised
Solution Approach 1:
Source/drain proximity is locally optimized for each device type: HPC devices receive aggressive proximity reduction for maximum speed, while SOC and IO devices maintain larger spacing to ensure reliability and prevent breakdown, with each region processed according to its specific performance requirements
3Reliability
If source/drain depth is increased to improve gate control, then short-channel effects are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The etch process is segmented into multiple steps with different parameters for different device regions. Each device type receives customized etch conditions that achieve the required source/drain depth with appropriate precision margins, reducing the overall manufacturing precision burden while maintaining effective gate control
Data Source
AI summary
Structures and methods for the co-optimization of various device types include performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in a first substrate region and a third source/drain recess for a third device in a third substrate region different than the first substrate region. In some embodiments, the method further includes performing a second photolithography and etch process to form a second source/drain recess for a second device in a second substrate region different than the first and third substrate regions. The method further includes forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.