FinFET Recessed Fin Insulation Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional FinFET manufacturing methods face challenges in maintaining electrical performance due to defects and improper design, particularly with Epi or silicide merging issues, which affect the size reduction trend in semiconductor devices.
Innovation Solution
The method involves forming a FinFET with a substrate having recessed fins and a gate stack, where an insulation layer with a lateral portion adjacent to the recessed fin and a central portion is created, ensuring the top surface of the lateral portion is higher than the central portion, preventing Epi or silicide merging and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional FinFET manufacturing methods are used, then device size can be reduced, but Epi or silicide merging occurs which degrades electrical performance
Solution Approach 1:
The insulation layer is segmented into a first insulation region and a second insulation region with different heights. The first insulation region has a higher top surface than the second insulation region, creating a stepped structure that physically separates adjacent Epi layers on recessed fins, preventing them from merging while maintaining device miniaturization.
Solution Approach 2:
Different regions of the insulation layer are given different local properties: the first insulation region under the gate stack has a higher height to provide isolation, while the second insulation region between gate stacks has a lower height to accommodate the recessed fin structure. This local differentiation prevents Epi merging without compromising overall device performance.
2Reliability
If insulation layer height is increased to prevent Epi merging, then electrical performance improves, but device complexity increases
Solution Approach 1:
The insulation layer is divided into two segments with different heights formed in different spatial regions. This segmentation allows the structure to provide enhanced isolation where needed (under gate stacks) while maintaining lower profiles in other areas (between gate stacks), balancing performance improvement with structural simplicity.
Solution Approach 2:
The solution addresses the Epi merging problem by introducing height variation in the vertical dimension rather than increasing lateral dimensions or adding more insulation layers. The stepped insulation structure uses vertical differentiation to achieve separation, avoiding increased device footprint or excessive structural complexity.
Data Source
AI summary
A fin field effect transistor (FinFET) with improved electrical performance and a method of manufacturing the same are disclosed. A FinFET includes a substrate having a top surface and an insulation. At least a recessed fin is extended upwardly from the top surface of the substrate, and at least a gate stack is formed above the substrate, wherein the gate stack is extended perpendicularly to an extending direction of the recessed fin, and the recessed fin is outside the gate stack. The insulation includes a lateral portion adjacent to the recessed fin, and a central portion contiguous to the lateral portion, wherein a top surface of the lateral portion is higher than a top surface of the central portion. A top surface of the recessed fin is lower than the top surface of the central portion of the insulation.