FinFET Recessed Liner Defines Fin Height
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Solution Overview
Problem
The existing process for forming FinFET devices often results in varying fin heights across the substrate due to timed etching and excessive dishing during chemical mechanical polishing, leading to inconsistent device performance and manufacturing challenges.
Innovation Solution
A liner recessing process is performed to define the fin height, involving multiple etching steps to form a conformal liner layer and a U-shaped liner structure, which allows for precise control of the fin height and uniformity across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If timed etching is used to form fins, then the fin height can be controlled by etch time, but the fin height varies across the substrate due to dishing and etch rate variations
Solution Approach 1:
A liner layer is formed on the substrate before the fin formation etching process. This liner layer serves as a sacrificial structure that is selectively removed to define the fin height. By performing this liner formation in advance, the fin height is predetermined by the liner thickness rather than by timed etching, which varies across the substrate.
Solution Approach 2:
The liner layer acts as an intermediary structure between the substrate and the fin formation process. It mediates the fin height definition by being selectively etched away, allowing precise control of fin height through the liner thickness which can be uniformly controlled during deposition, rather than through timed etching which suffers from dishing and rate variations.
2Shape
If chemical mechanical polishing is used to planarize the substrate, then surface flatness is improved, but excessive dishing occurs that affects subsequent fin height control
Solution Approach 1:
The liner layer is formed on the substrate before the chemical mechanical polishing step. This ensures that the liner is present to define the fin height reference plane even after polishing-induced dishing occurs. The liner thickness, deposited before polishing, remains uniform and serves as the ultimate fin height reference regardless of subsequent substrate surface variations.
3Quantity of substance
If fin pitch is reduced to increase device density, then more devices fit on the chip, but fin height control becomes more difficult due to proximity effects
Solution Approach 1:
The liner layer provides a locally-defined reference plane for each fin region. Since the liner is conformally deposited and its thickness is controlled by the deposition process rather than etching, each fin region has its own locally-defined height reference that is independent of neighboring fins. This allows dense fin pitch while maintaining uniform fin height control through the liner-based reference system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent fin heights and improved manufacturing reliability by controlling the fin height independently of fin pitch, enhancing device performance and simplifying subsequent processing steps.
Implementation Method 1
performing at least one first etching process through a patterned hard mask layer to form a plurality of trenches in a semiconducting substrate
Implementation Method 2
excessive dishing during chemical mechanical polishing
Data Source
AI summary
One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.