FinFET Recessed Source-Drain Regions Reduce Parasitic Capacitance
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Solution Overview
Problem
FinFET devices suffer from increased parasitic capacitance and access resistance, which reduces their performance, and existing attempts to decrease parasitic capacitance often result in increased access resistance.
Innovation Solution
The formation of recessed source-drain regions within the buried oxide of the finFET device, along with the use of longer silicide contact lengths and closer stress liner proximity, reduces parasitic capacitance and access resistance while improving stress coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional FinFET structure is used, then device functionality is achieved, but parasitic capacitance and access resistance increase
Solution Approach 1:
The patent introduces a vertical dimension by etching recesses into the source and drain regions below the gate level. This dimensional change separates the conductive path from the gate electrode, reducing the overlapping area and thus the parasitic capacitance between gate and source/drain, while maintaining horizontal electrical connectivity through the recessed regions
2Object-affected harmful factors
If recessed source-drain regions are formed, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The recesses are formed in the source and drain regions before the final metallization and contact formation steps. This preliminary action allows subsequent processing layers to conformally fill the recesses, simplifying the overall fabrication by integrating the capacitance reduction feature into earlier process steps rather than requiring additional complex post-processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and access resistance, enhancing the performance of finFET devices by creating a more efficient conducting path and reducing contact resistance.
Implementation Method 1
The method dopes the fin to form extension junctions. Each extension junction extends under the gate
Implementation Method 2
The method forms a silicide layer on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers
Data Source
AI summary
A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each second spacer is adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.