Selective Strain Control in FinFET Transistor Channels
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Solution Overview
Problem
Current semiconductor technologies face challenges in fabricating n-type and p-type metal-oxide-semiconductor field effect transistors with different stress states in a common layer on a semiconductor substrate, as existing methods struggle to efficiently alter strain states in specific regions without affecting adjacent areas, which impacts the mobility and performance of transistors.
Innovation Solution
A method involving a multi-layer substrate with a buried oxide layer and an epitaxial base layer, where elements are diffused into the strained primary semiconductor layer in one region without affecting another, allowing for the formation of transistor channel structures with distinct strain states, enabling the fabrication of n-type and p-type transistors with optimized electron and hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If elements are diffused into the strained primary semiconductor layer in one region, then the strain state in that region is altered to improve transistor performance, but the diffusion process may unintentionally affect adjacent regions and alter their strain states
Solution Approach 1:
The substrate is divided into multiple discrete regions (first region, second region, third region) with different strain states. Each region can be independently processed to achieve different strain conditions, allowing precise control over transistor characteristics in different areas of the device.
Solution Approach 2:
Different regions of the semiconductor layer are given different strain states (tensile, compressive, or relaxed) tailored to the specific transistor type (n-type or p-type) that will be formed in each region. This local differentiation optimizes electron mobility in n-type regions and hole mobility in p-type regions independently.
2Device complexity
If a common semiconductor layer is used for both n-type and p-type transistors, then device integration is simplified, but the conflicting strain state requirements for n-type (tensile) and p-type (compressive) transistors cannot be simultaneously satisfied
Solution Approach 1:
The common semiconductor layer is segmented into multiple regions, each with independently controlled strain states. This allows a single layer structure to serve multiple transistor types by creating spatially differentiated strain zones through selective element diffusion in different regions.
Solution Approach 2:
The strain state parameter of the semiconductor layer is changed locally by controlling the concentration and type of diffused elements (such as carbon or oxygen) in different regions. By adjusting these compositional parameters, the lattice constant and strain state are modified to match the requirements of different transistor types within the same layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the selective alteration of strain states in semiconductor layers, enhancing the performance of NMOS and PMOS transistors by improving electron and hole mobility, and enabling the production of transistors with varying stress states in a common layer, thereby improving the electrostatic performance and reducing threshold voltage.
Implementation Method 1
Elements are diffused from the epitaxial base layer into the strained primary semiconductor layer within a first region of the multi-layer substrate
Data Source
AI summary
Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.