FinFET Replacement Gate Structure with Reduced Channel Fin Size
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of feature sizes in semiconductor devices leads to increased resistance and reduced operational performance due to the physical size reduction of fins outside the channel region during the replacement gate process, resulting in undesirable short channel effects and increased power consumption.
Innovation Solution
The method involves forming a fin protection layer around the fin, creating a sacrificial gate electrode, forming sidewall spacers, removing the sacrificial gate to expose the fin protection layer, oxidizing the exposed portion, and then removing the oxidized layer to form a replacement gate structure, which helps in reducing the fin size within the channel region and minimizing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fin size is reduced to increase transistor density, then the number of transistors per chip area increases, but the resistance increases and operational performance deteriorates
Solution Approach 1:
The patent applies local quality by creating different fin dimensions in different regions: the channel region maintains larger fin dimensions for optimal transistor performance, while the source/drain regions have reduced fin dimensions to increase transistor density. This is achieved through selective etching processes that modify fin dimensions in specific areas, allowing each region to have the optimal characteristics for its function.
2Productivity
If the fin size is reduced outside the channel region, then transistor density increases, but short channel effects increase and power consumption increases
Solution Approach 1:
The patent implements local quality by preserving larger fin dimensions in the channel region while reducing fin dimensions in the source/drain regions. This selective dimension control minimizes short channel effects in the channel where they are most critical, while still achieving increased transistor density through the reduced dimensions in the source/drain regions.
Solution Approach 2:
The fin structure is segmented into different regions with different dimensions: the channel region fins and the source/drain region fins have different sizes. This segmentation allows independent optimization of each region, maintaining performance in the channel while maximizing density in the source/drain areas.
3Productivity
If the fin size is reduced to increase transistor density, then more transistors fit in the chip area, but resistance increases
Solution Approach 1:
The patent applies local quality by maintaining larger fin dimensions in the channel region where resistance control is critical, while reducing fin dimensions in the source/drain regions where density is the priority. This selective approach allows resistance to be controlled where it matters most while still achieving high overall transistor density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the fin size within the channel region, thereby reducing short channel effects and improving operational performance by minimizing resistance and power consumption.
Implementation Method 1
oxidizing the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.