FinFET Replacement Gate Process for Self-Aligned Source Drain Contact
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Solution Overview
Problem
FinFET devices face challenges in accurately and consistently contacting source and drain regions due to the difficulty in aligning landing pads with the gate, and existing solutions like epitaxial processes are sensitive to surface chemistry and require precise control, while also struggling with scalability as feature sizes decrease.
Innovation Solution
A method involving a semiconductor-on-insulator wafer with fin hardmasks, a dummy gate, and a replacement gate process where doping agents are implanted and activated before forming the replacement gate, allowing for self-aligned source and drain regions and precise fin formation within a trench, enabling consistent and scalable FinFET device fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If landing pads are used to contact the fins, then mechanical stability during processing is improved and device contacting scheme is simplified, but precise alignment with the gate becomes difficult and parasitic capacitance increases
Solution Approach 1:
The patent removes the landing pad structure entirely from the device architecture. Instead of using separate landing pads for contacting fins, the invention implements direct contact to the fins through contact holes formed in the interlayer dielectric, eliminating the alignment complexity and parasitic capacitance associated with landing pads while maintaining manufacturing simplicity
Solution Approach 2:
The gate electrode structure serves multiple functions: it acts as the control electrode for the FinFET and simultaneously provides the reference alignment feature for contact hole formation. The self-aligned process uses the gate itself as the masking structure, eliminating the need for separate landing pads and achieving both simplification and precision
2Reliability
If epitaxial processes are used to form source and drain regions, then series resistance is reduced and contacting scheme is simplified, but sensitivity to surface chemistry and crystal orientation increases and process control becomes more difficult
Solution Approach 1:
The patent uses ion implantation to form source and drain regions instead of epitaxial growth. This approach uses a simpler, more robust process that is less sensitive to surface chemistry and crystal orientation. The ion implantation process is well-established, easier to control, and does not require the extreme precision of epitaxial processes while still achieving low resistance contacts
Solution Approach 2:
The invention changes the fundamental approach from epitaxial growth (which requires precise control of temperature, pressure, and gas flow) to ion implantation followed by rapid thermal annealing. This parameter change simplifies the process while maintaining or improving contact reliability, as ion implantation is less sensitive to surface conditions and can be precisely controlled through dose and energy parameters
3Manufacturing precision
If fins are formed before gate patterning, then fin pitch can be controlled, but thin fins must survive aggressive etching processes during gate and spacer processing
Solution Approach 1:
The patent forms the gate structure first using a dummy gate, then uses this gate as a mask to define the fin regions through anisotropic etching. This preliminary action establishes the gate position and protects it during subsequent processing, while the fin etching is performed in a controlled manner that preserves fin integrity. The gate serves as a protective mask during the fin formation process
Solution Approach 2:
The fabrication process is segmented into distinct stages: first forming the gate structure with dummy gate, then forming fins in the exposed regions, and finally replacing the dummy gate with the actual gate material. This segmentation allows each structure to be formed under optimized conditions without interfering with the other, maintaining both fin pitch control and fin integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and consistent formation of FinFET devices with self-aligned source and drain regions, improving contact reliability and scalability, reducing parasitic capacitance and resistance, and allowing for narrower feature sizes without the sensitivity issues of epitaxial processes.
Implementation Method 1
One or more doping agents are implanted into the source and drain regions
Implementation Method 2
The doping agents implanted into the source and drain regions are activated using rapid thermal annealing
Data Source
AI summary
FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.