FinFET Replacement Gate Recess to Reduce Punch Through Leakage
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Solution Overview
Problem
FinFET semiconductor devices experience significant punch through leakage currents, particularly at the bottom of the fins near local isolation regions, which degrade device performance and are challenging to mitigate effectively.
Innovation Solution
The method involves forming trenches in a semiconducting substrate to create fin structures, followed by the formation of local isolation regions and a sacrificial gate structure. After removing the sacrificial gate, a replacement gate structure is inserted into a recess in the local isolation region and gate cavity, extending further along the fins to reduce leakage currents without degrading mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of FETs is decreased to improve switching speed and increase device density, then the operating speed and density are improved, but the separation between source and drain regions is reduced, making it difficult to inhibit the electrical potential of the channel from being adversely affected by the drain potential, resulting in short channel effects
Solution Approach 1:
The patent transitions from a planar FET structure to a FinFET structure with a vertically positioned fin-shaped active area. The gate electrode encloses both sides and the upper surface of the fin, creating a three-dimensional structure where the channel is formed perpendicular to the substrate surface. This dimensional change increases the effective channel length without increasing the planar footprint, thereby improving control over the channel potential and reducing short channel effects while maintaining high device density.
Solution Approach 2:
The FinFET structure segments the channel into multiple controlled surfaces (two sidewalls and one top surface) that are all enclosed by the gate electrode. This segmentation allows the gate to exert control over the channel potential from multiple directions, effectively抑制ing the drain-induced barrier lowering and reducing short channel effects even at reduced channel lengths.
2Reliability
If FinFET devices are used to reduce depletion width and short channel effects, then the junction capacitance is reduced and short channel effects are mitigated, but punch through leakage currents still occur, particularly at the bottom of the fins proximate to local isolation regions
Solution Approach 1:
The patent performs preliminary oxidation of the fin bottom region before forming the gate structure. This preliminary action creates a region of depleted carriers at the fin bottom that acts as a barrier to punch through leakage currents. By addressing the leakage issue before final device assembly, the structure is pre-configured to resist harmful currents while maintaining the FinFET's short channel effect reduction benefits.
Solution Approach 2:
The patent applies selective oxidation to the fin bottom region, creating a localized modification with different electrical properties. This local quality change increases the resistance to punch through leakage currents specifically at the critical fin-bottom region near local isolation structures, without affecting the overall FinFET performance or requiring complex global process modifications.
3Object-generated harmful factors
If conventional methods are used to reduce punch through leakage currents by implanting or oxidizing the bottom portion of fins to merge local isolation regions, then leakage currents are reduced, but the process complexity increases significantly
Solution Approach 1:
The patent merges the oxidation step into the existing gate formation process sequence. The fin bottom oxidation is performed as part of the standard gate stack fabrication流程, combining what would otherwise be a separate, complex implantation or post-processing step with the routine gate formation operations. This integration reduces process complexity while achieving effective leakage current reduction.
Solution Approach 2:
The oxidation process naturally extends to the fin bottom regions during the gate formation sequence, utilizing the same processing conditions and chemistry that would be applied to other device regions. The structure itself guides the oxidation to occur where needed (at the fin bottoms near isolation regions) without requiring additional masking or patterning steps, allowing the process to self-organize and reduce complexity.
Data Source
AI summary
One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.