FinFET Self-Aligned Contacts via Replacement Gate and Silicide
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Solution Overview
Problem
The formation of self-aligned contacts in FinFET semiconductor devices using a replacement gate process results in undesirable loss of protective gate cap layers and sidewall spacers, leading to increased complexity and difficulty in gate and spacer etching processes, and poses challenges in maintaining sufficient thickness to prevent short circuits and optimize packing density.
Innovation Solution
The method involves forming a sacrificial gate structure, epitaxial deposition to merge fins, removing the sacrificial gate, and forming a replacement gate structure, followed by a metal silicide layer on the source/drain regions, and simultaneously creating source/drain and gate contact structures with dimensions optimized to reduce the risk of short circuits and minimize device footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If self-aligned contacts are formed in FinFET devices using replacement gate process, then contact alignment precision is improved, but protective gate cap layers and sidewall spacers are lost
Solution Approach 1:
The patent applies preliminary action by forming the gate cap layer and sidewall spacers before the contact etching process, and performing the contact etch through these protective structures. This preliminary preparation of protective layers enables subsequent self-aligned contact formation while maintaining layer integrity throughout the process.
2Reliability
If gate cap layer and sidewall spacers are made thicker to prevent short circuits, then short circuit risk is reduced, but device footprint increases
Solution Approach 1:
The patent changes the parameter of protective layer thickness by forming the gate cap layer and sidewall spacers with optimized dimensions that provide sufficient protection against short circuits while maintaining compact device footprint. The self-aligned contact process enables this optimization by eliminating the need for excessive thickness margins.
3Manufacturing precision
If complex etching processes are used to form contacts, then contact formation precision is improved, but process complexity increases
Solution Approach 1:
The patent applies self-service through the self-aligned contact process where the gate structure automatically serves as the alignment reference for contact formation. The gate cap layer and sidewall spacers self-align with the fin structures, eliminating the need for complex external alignment procedures and reducing overall process complexity while maintaining high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of short circuits, allows for more precise alignment of contact structures, and decreases the device footprint, thereby enhancing packing density and operational efficiency while maintaining sufficient protection for the gate structures.
Implementation Method 1
performing an epitaxial deposition fin-merger process to form a plurality of merged-fin regions that define a plurality of source/drain regions for the transistor
Implementation Method 2
forming a metal silicide layer on an entire upper surface area of each of the plurality of source/drain regions
Data Source
AI summary
One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction.